Connection Problem in 10 Gbit UDP, IP and ARP Supported Design

[adnanakcan]

Hello,
In my Verilog based Ethernet project, I implemented a 10 Gbit UDP, IP and ARP supported stack design on a Kintex-7 FPGA card using the NetFPGA_SUME example. In this design, I can successfully perform Echo Reply operations with Xilinx 10G PCS/PMA IP CORE. IP CORE uses Xilinx GTX transceiver for data communication at the lower level.
However, in order to simplify my design, I aim to make a successful design by using eth_phy_10g module instead of Xilinx 10G PCS/PMA IP CORE and adding only GT Wizard IP Core. I think I have made the necessary corrections to make these changes, but I noticed that the connection cannot be established with the Intel X520-DA2 10GBE Dual Port SFP+ Ethernet Card connected to my desktop computer.
Here, I am sharing the Verilog codes of my FPGA upper module, eth_phy_10g module and GT Wizard IP Core. I am also adding the configuration screenshots of GT Wizard IP Core.
I would be very happy if you can help me.
Thank you.

module eth_phy_10g.txt
module fpga.txt
module gtwizard_0.txt