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0166-2023-10-26.md

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26 Oct 2023

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Preparing for chipIgnite

  • See if we can make sure that la_oenb detection can tell us when to stay in reset.
  • Do we need to assign anything to io_out, when using the respective IO as an input, in order to ensure its input will be sensed properly? i.e. does it affect pull-ups or anything?
  • If we ACTUALLY try to invalidly synth logic inside UPW, will we get a warning/error or silent failure? Any other way to detect dodgy business?
  • This is an approach I started using for my top module, to make it look more like caravel, but in the end I abandoned it because it is less flexible, and probably not necessary. I will keep it here in case Matt tells me it is needed, but otherwise I can't see how Matt's own mux would be able to work without the ability to do some wires: 
    module top_ew_algofoogle(                   // Typically connected to...
    input   wire        i_anton_clock,      // - user_clock2
    input   wire [8:0]  i_anton_io_in,      // - io_in[26:18]
    output  wire [8:0]  o_anton_io_out,     // - io_out[26:18]
    output  wire [8:0]  o_anton_io_oeb,     // - io_oeb[26:18] (we drive this)
    input   wire [50:0] i_anton_la_in,      // - la_in[114:64]
    output  wire [50:0] o_anton_la_out,     // - la_out[114:64] // UNUSED
    input   wire [50:0] i_anton_la_oenb,    // - la_oenb[114:64] (SoC drives this)
    output  wire [2:0]  o_anton_irq         // - user_irq[2:0]
);

    wire    i_clk               = i_anton_clock;
    wire    i_reset_lock_a      = i_anton_la_in[0];
    wire    i_reset_lock_b      = i_anton_la_in[1];
    assign  o_anton_io_out[0]   = o_hsync;              wire o_hsync;
    assign  o_anton_io_out[1]   = o_vsync;              wire o_vsync;
    assign  o_anton_io_out[2]   = o_tex_csb;            wire o_tex_csb;
    assign  o_anton_io_out[3]   = o_tex_sclk;           wire o_tex_sclk;
    assign  o_anton_io_out[4]   = o_tex_out0;           wire o_tex_out0;
    assign  o_anton_io_oeb[4]   = o_tex_oeb0;           wire o_tex_oeb0;
    wire [3:0] i_tex_in = {
        i_anton_la_in[50],
        anton_io_in[8],
        anton_io_in[7],
        anton_io_in[4]
    };

    ...

endmodule
  • Polarity of io_oeb and la_oenb remain unclear to me:
    • OHHH, la_oenb is itself an INPUT, which means it is the SoC telling our design when we should be reading it.
  • Make sure if LAs are NOT being driven by SoC, that they mux to a sensible value (e.g. 0).
  • Use pin configuration to ensure LA pins end up on a sensible side, and maybe suited to where the IOs need to be to route to pads.
  • Update to latest version of caravel (CUP?)
  • Slim down my snippets. Don't overdo it! Put the comments elsewhere and reference them.
  • Group call with Ellen, Pawel, Matt on Monday, 2023-10-30, at 17:00 BST (British Summer Time). For me, that's 2023-10-31 (Tuesday) at 03:30am.
    • Points for discussion:
      • Pin placement: My IOs on the same side where they will be needed? Or someone can just mirror my macro.
      • Sharing stuff: Digital only? Inputs only? What about analog?
      • Can our designs simply share digital inputs such that they don't need a mux? i.e. my design needs up to 3 digital inputs, and so does Ellen's, so can those drive both of our designs simultaneously, especially since our designs are otherwise independent?
      • GPIO config defaults
      • Does it matter which LA numbers I use?
      • Can I use the 'user maskable interrupt signals' (user_irg[2:0])? I could use hblank and vblank outputs.
      • You can't synth logic in the UPW level, right? Does this include constants (i.e. 1'b0 or 1'b1 which tend to synth to con cells)? In other words, MUST I make sure that any such constant assignments are only ever done within the module I'm instantiating? This goes both for things like: assign la_oenb[90:40] = 51'b111....0 ; and .o_rgb({ bb,6'bzzzzzz, gg,6'bzzzzzz, rr'6bzzzzzz }) ; and .i_tex_in({1'b0, ...}) ; and .o_gpout({4'bzzzz, ...}).
      • Why not upper 2 GPIOs (36 and 37)? These can't do analog, but are they otherwise fine as digital? Do they have any other special function? Reserved for Ellen maybe?
      • Comment out: 
        # don't put clock buffers on the outputs, need tristates to be the final cells
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
      • Analog: Is it better to include my DAC as an extra macro and instantiate that to join with both analog_io and my main macro's rgb pins, or just embed the DAC as a macro within my main macro, and have it provide its output as an inout port and map that to analog_io? What do we need to do with power?
  • For now, my GDS/LEF, etc are in raybox-zero-gds@ew
  • I've written a spec for how my design is expected to make use of Caravel and other shared resources: EWSPEC
  • In config.tcl commented out this, because my design doesn't have actual tristate signals: 
    # don't put clock buffers on the outputs, need tristates to be the final cells
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
  • Placement macro (macro.cfg) will be up to Ellen or Matt.
  • Does user_project_wrapper.v represent the whole Caravel user area, or something smaller within?

Goals

  • Create different snippets based on actual number of IOs (inc. muxed). Put each separate version under respective heading in EWSPEC... but as for supplied files, where should they go? All in one, or 3 separate snippet files?
  • Should my instantiated design handle assignment of all constants too, i.e. just make sure all LAs and IOs and OEBs go directly into my top-level design, and it can assign STATIC OEB's as well as the variable ones?
  • Try doing someting like this: 
    // To help with moving around Anton's pads and LAs, this convenience mapping
// can be changed easily without needing to edit the instantiation below:
wire [8:0] anton_ext_pads = ...
  • Ellen has recommended using user_clock2 and specific nominated IO nets (see comment from 2023-10-26 00:28): GPIOs 18-26 (zero-based numbering).
  • Make instantiation snippet(s) for Ellen in raybox-zero repo. They should cover constants, e.g. decide on what floating inputs should be if not part of a mux; and if we can't have 51 LAs, include a comment for pulling excess pins low.
  • Could go thru this guide to do the harden and wiring?
  • Do we need power signals too?? e.g. this
  • Put the snippet in EWSPEC.
  • NOTE: The snippet might need to be rewritten if I am confident about my analog outputs! e.g. 9-pin version would change from 2 gpout, to 1 gpout and 1 analog.
  • Implement LA OEBs, etc.
  • Check Pawel's note about GPIO_MODE_USER_STD_ANALOG and oeb[].
  • Include ports for muxing??
  • Default Caravel IO config snippet for my IOs
  • Review Z2A Part 5 guide on hardening for UPW
  • Supply files in the right format and structure -- which repo?
  • No need for final buffer removal? Or is there still if using Matt's mux?
  • Watch video
  • Try newer OpenLane even if just for better verification inc. CVC
  • Reset line should disable SCLK inverter/CTS?
  • Check how inverted SCLK flows thru cells: Is it actually inverted or cells use negedge clocking from main clock instead? Does it still get CTS?
  • Review 2310C, optionally add to it
  • Test TOP on FPGA
  • Use generate in top_ew_algofoogle for gpout muxes
  • Check firmware and register doco for SoC re PLL and LA
  • Fix missing images (and anything else?) from 0165.