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- While a WB mux would've been nice, I want to stick to what I know and understand right now. Thus, I will first try an LA-controlled mux. There's something key though:
- I want reset to be driven by wb_rst_i, because I don't trust using an LA pin for reset (given timing issues). I will still have one, but want wb_rst_i to still work.
- The problem is that wb_rst_i is the system reset, which will also reset the LA, so the mux needs to survive that. Hence, it probably needs some registers.
NOTE: Most of this is actually from 2023-12-07.
I've started working on a mux for a team GFMPW-1 submission.
For now it's pretty basic. It works as follows:
- It connects directly to all 38 io_outs, and io_oebs.
- It has input ports for the specific output/oeb signals that come from each design. Currently such an interface is only implemented for top_raybox_zero_fsm.
- There are 5 LA lines it uses: 4 bits to identify the design that should become active (one of 16), and 1 to clock in (i.e. register, on rising edge) that ID and actually activate the design (i.e. connect it to the IO outputs/oebs).
- NOTE: That registered design ID intentionally has no reset, because I want it to be possible to then actually assert
wb_rst_iand NOT lose the design that has already been selected.
I have so far successfully hardened UPW (using this commit) with both top_design_mux and top_raybox_zero_fsm. The results are interesting.
Observations about the below summary (assuming we can trust these figures without a complete SDC for every port of the mux):
- Max slews are improved.
- Max caps are improved.
- Antennas are terrible.
I suspect one of the problems with antennas is that the current pin ordering for TRZF is poor. Areas for improvement:
- Line up TRZF pins much better with the mux and LAs.
- Consider taking
io_ins into the mux, and then fanning them out to each design. - OR: Try to ensure that all
io_ins for TRZF, are clustered on the side which is nearest some IO pads (which means renumbering too). In this case specifically, because TRZF is currently in the SE corner, we'd need to skip IO[7:0] and use (say) IO[24:8] (though this goes all the way up to the NW corner anyway).
Latest UPW run: >>> 23_12_07_21_45 <<< (openlane/user_project_wrapper/runs/23_12_07_21_45)
| Design final GDS size | 28M (28437098) |
| Design macro dimensions | 2956x2952 |
| (summary.py temp run num) | 14 |
| Flow success | Yes |
| total_runtime | 0:3:16 |
| FP_CORE_UTIL | 50 |
| PL_TARGET_DENSITY | 0.6 |
| OpenDP_Util | -1% |
| synth_cell_count | 2 |
| net_antenna_violations | 31 |
| wns | 0.0 |
| tns | 0.0 |
| cells_pre_abc | 2 |
| CoreArea_um | 8724457.9968 |
| NonPhysCells | 2 |
| CLOCK_PERIOD | 40 |
Setup, slews, caps: openlane/user_project_wrapper/runs/23_12_07_21_45/reports/signoff/*-sta-rcx_nom/multi_corner_sta.checks.rpt
Unconstrained:
Path Type: max
2.99 slack (MET)
slack_max:
No paths found.
Slew, caps, fanout:
max slew violations count Typical: 6
max fanout violations count Typical: 36
max cap violations count Typical: 2
Max slew:
Pin Limit Slew Slack
------------------------------------------------------------
top_design_mux/input11/I 3.00 4.92 -1.92 (VIOLATED)
top_design_mux/ANTENNA_input11_I/I 3.00 4.92 -1.92 (VIOLATED)
top_raybox_zero_fsm/output33/Z 3.00 4.91 -1.91 (VIOLATED)
top_design_mux/input22/I 3.00 3.93 -0.93 (VIOLATED)
top_design_mux/ANTENNA_input22_I/I 3.00 3.93 -0.93 (VIOLATED)
top_raybox_zero_fsm/output44/Z 3.00 3.92 -0.92 (VIOLATED)
Showing all 6
Fanout:
Pin Limit Fanout Slack
---------------------------------------------------------
Pin Limit Cap Slack
------------------------------------------------------------
top_raybox_zero_fsm/clkbuf_5_21__f_i_clk/Z 10 32 -22 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_31__f_i_clk/Z 10 32 -22 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_20__f_i_clk/Z 10 30 -20 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_29__f_i_clk/Z 10 28 -18 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_26__f_i_clk/Z 10 26 -16 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_24__f_i_clk/Z 10 24 -14 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_7__f_i_clk/Z 10 24 -14 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_18__f_i_clk/Z 10 22 -12 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_23__f_i_clk/Z 10 22 -12 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_30__f_i_clk/Z 10 22 -12 (VIOLATED)
Showing worst 10 out of 38
Max caps:
Pin Limit Cap Slack
------------------------------------------------------------
top_raybox_zero_fsm/output33/Z 0.24 0.31 -0.07 (VIOLATED)
top_raybox_zero_fsm/output44/Z 0.24 0.24 -0.01 (VIOLATED)
Showing all 2
Hold slack: openlane/user_project_wrapper/runs/23_12_07_21_45/reports/signoff/*-sta-rcx_nom/multi_corner_sta.min.rpt
worst slack corner Typical: 0.5395
Antennas: openlane/user_project_wrapper/runs/23_12_07_21_45/reports/signoff/*-antenna_violators.rpt
Partial/Required: 7.64, Required: 400.0, Partial: 3057.21, Net: io_in[30], Pin: top_raybox_zero_fsm/i_debug_trace_overlay, Layer: Metal5
Partial/Required: 7.61, Required: 400.0, Partial: 3042.66, Net: io_in[28], Pin: top_raybox_zero_fsm/i_debug_vec_overlay, Layer: Metal5
Partial/Required: 7.41, Required: 400.0, Partial: 2964.89, Net: io_in[31], Pin: top_raybox_zero_fsm/i_reg_outs_enb, Layer: Metal5
Partial/Required: 7.29, Required: 400.0, Partial: 2916.34, Net: io_in[27], Pin: top_raybox_zero_fsm/i_reg_mosi, Layer: Metal5
Partial/Required: 6.90, Required: 400.0, Partial: 2761.93, Net: io_in[29], Pin: top_raybox_zero_fsm/i_debug_map_overlay, Layer: Metal5
Partial/Required: 4.94, Required: 400.0, Partial: 1976.01, Net: io_in[32], Pin: top_raybox_zero_fsm/i_mode[0], Layer: Metal5
Partial/Required: 4.88, Required: 400.0, Partial: 1950.94, Net: io_in[34], Pin: top_raybox_zero_fsm/i_mode[2], Layer: Metal5
Partial/Required: 3.43, Required: 400.0, Partial: 1371.09, Net: io_in[24], Pin: top_raybox_zero_fsm/i_vec_mosi, Layer: Metal3
Partial/Required: 3.32, Required: 400.0, Partial: 1327.73, Net: io_in[26], Pin: top_raybox_zero_fsm/i_reg_sclk, Layer: Metal3
Partial/Required: 3.10, Required: 400.0, Partial: 1241.05, Net: io_in[33], Pin: top_raybox_zero_fsm/i_mode[1], Layer: Metal5
Showing worst 10 out of 41
After reordering pins and messing around with SDC, these are the results I got, but I have no idea if they're real... they seem too good to be true:
Latest design run: >>> 23_12_08_00_22 <<< (openlane/top_raybox_zero_fsm/runs/23_12_08_00_22)
| Design final GDS size | 24M (24905814) |
| Design macro dimensions | 800x800 |
| (summary.py temp run num) | 16 |
| Flow success | Yes |
| total_runtime | 0:14:9 |
| FP_CORE_UTIL | 49 |
| PL_TARGET_DENSITY | 0.55 |
| OpenDP_Util | 50.43% |
| synth_cell_count | 14470 |
| net_antenna_violations | 1 |
| wns | 0.0 |
| tns | 0.0 |
| cells_pre_abc | 15694 |
| CoreArea_um | 639488.1024 |
| NonPhysCells | 15380 |
| CLOCK_PERIOD | 39 |
Setup, slews, caps: openlane/top_raybox_zero_fsm/runs/23_12_08_00_22/reports/signoff/*-sta-rcx_nom/multi_corner_sta.checks.rpt
Unconstrained:
Path Type: max
1.78 slack (MET)
slack_max:
No paths found.
Slew, caps, fanout:
max slew violations count Typical: 4
max fanout violations count Typical: 1481
max cap violations count Typical: 0
Max slew:
Pin Limit Slew Slack
------------------------------------------------------------
o_tex_sclk 3.00 3.11 -0.11 (VIOLATED)
output44/Z 3.00 3.11 -0.11 (VIOLATED)
o_gpout[2] 3.00 3.10 -0.10 (VIOLATED)
output33/Z 3.00 3.10 -0.10 (VIOLATED)
Showing all 4
Fanout:
Pin Limit Fanout Slack
---------------------------------------------------------
clkbuf_5_16__f_i_clk/Z 4 30 -26 (VIOLATED)
clkbuf_5_21__f_i_clk/Z 4 28 -24 (VIOLATED)
clkbuf_5_23__f_i_clk/Z 4 28 -24 (VIOLATED)
clkbuf_5_3__f_i_clk/Z 4 28 -24 (VIOLATED)
clkbuf_5_5__f_i_clk/Z 4 26 -22 (VIOLATED)
clkbuf_5_0__f_i_clk/Z 4 24 -20 (VIOLATED)
clkbuf_5_1__f_i_clk/Z 4 22 -18 (VIOLATED)
clkbuf_5_28__f_i_clk/Z 4 22 -18 (VIOLATED)
clkbuf_5_2__f_i_clk/Z 4 22 -18 (VIOLATED)
clkbuf_5_6__f_i_clk/Z 4 22 -18 (VIOLATED)
Showing worst 10 out of 1481
Max caps:
None
Hold slack: openlane/top_raybox_zero_fsm/runs/23_12_08_00_22/reports/signoff/*-sta-rcx_nom/multi_corner_sta.min.rpt
worst slack corner Typical: 0.3956
Antennas: openlane/top_raybox_zero_fsm/runs/23_12_08_00_22/reports/signoff/*-antenna_violators.rpt
Partial/Required: 1.36, Required: 400.0, Partial: 545.96, Net: _10609_, Pin: _17249_/I, Layer: Metal2
Showing all 1
Step: UPW
Latest UPW run: >>> 23_12_08_00_36 <<< (openlane/user_project_wrapper/runs/23_12_08_00_36)
| Design final GDS size | 28M (28529160) |
| Design macro dimensions | 2956x2952 |
| (summary.py temp run num) | 9 |
| Flow success | Yes |
| total_runtime | 0:3:15 |
| FP_CORE_UTIL | 50 |
| PL_TARGET_DENSITY | 0.6 |
| OpenDP_Util | -1% |
| synth_cell_count | 2 |
| net_antenna_violations | 36 |
| wns | 0.0 |
| tns | 0.0 |
| cells_pre_abc | 2 |
| CoreArea_um | 8724457.9968 |
| NonPhysCells | 2 |
| CLOCK_PERIOD | 40 |
Setup, slews, caps: openlane/user_project_wrapper/runs/23_12_08_00_36/reports/signoff/*-sta-rcx_nom/multi_corner_sta.checks.rpt
Unconstrained:
Path Type: max
2.93 slack (MET)
slack_max:
No paths found.
Slew, caps, fanout:
max slew violations count Typical: 0
max fanout violations count Typical: 36
max cap violations count Typical: 0
Max slew:
Showing all 1
Fanout:
Pin Limit Fanout Slack
---------------------------------------------------------
top_raybox_zero_fsm/clkbuf_5_16__f_i_clk/Z 10 30 -20 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_21__f_i_clk/Z 10 28 -18 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_23__f_i_clk/Z 10 28 -18 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_3__f_i_clk/Z 10 28 -18 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_5__f_i_clk/Z 10 26 -16 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_0__f_i_clk/Z 10 24 -14 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_1__f_i_clk/Z 10 22 -12 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_28__f_i_clk/Z 10 22 -12 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_2__f_i_clk/Z 10 22 -12 (VIOLATED)
top_raybox_zero_fsm/clkbuf_5_6__f_i_clk/Z 10 22 -12 (VIOLATED)
Showing worst 10 out of 36
Max caps:
None
Hold slack: openlane/user_project_wrapper/runs/23_12_08_00_36/reports/signoff/*-sta-rcx_nom/multi_corner_sta.min.rpt
worst slack corner Typical: 0.5456
Antennas: openlane/user_project_wrapper/runs/23_12_08_00_36/reports/signoff/*-antenna_violators.rpt
Partial/Required: 3.51, Required: 400.0, Partial: 1405.99, Net: wb_rst_i, Pin: top_raybox_zero_fsm/i_reset, Layer: Metal3
Partial/Required: 2.82, Required: 400.0, Partial: 1129.56, Net: io_in[29], Pin: top_design_mux/io_in[29], Layer: Metal3
Partial/Required: 2.39, Required: 400.0, Partial: 954.17, Net: io_in[31], Pin: top_design_mux/io_in[31], Layer: Metal3
Partial/Required: 2.38, Required: 400.0, Partial: 953.79, Net: io_in[33], Pin: top_design_mux/io_in[33], Layer: Metal3
Partial/Required: 2.38, Required: 400.0, Partial: 953.01, Net: io_in[30], Pin: top_design_mux/io_in[30], Layer: Metal3
Partial/Required: 2.38, Required: 400.0, Partial: 951.46, Net: io_in[32], Pin: top_design_mux/io_in[32], Layer: Metal3
Partial/Required: 2.36, Required: 400.0, Partial: 945.05, Net: io_in[9], Pin: top_design_mux/io_in[9], Layer: Metal3
Partial/Required: 2.34, Required: 400.0, Partial: 936.75, Net: io_in[3], Pin: top_design_mux/io_in[3], Layer: Metal3
Partial/Required: 2.34, Required: 400.0, Partial: 936.36, Net: io_in[4], Pin: top_design_mux/io_in[4], Layer: Metal3
Partial/Required: 2.24, Required: 400.0, Partial: 894.85, Net: io_in[5], Pin: top_design_mux/io_in[5], Layer: Metal3
Showing worst 10 out of 40
I need to check the signoff.sdc, I guess...?
- Check/fix SDC for mux.
trzf_*ports don't yet have any constraints. - Do a very simple proof-of-life macro, maybe one on the mux, and another bypassing the mux
- Do a simple WB design (since I think it can be shared without muxing?)
- Get rid of a0s and a1s. No longer needed.
- Work out where we want TRZF to source its clock.
- It might be too far to route from wb_clk_i.
- It will be pretty close to user_clock2, but we want to make sure that one is OK. Switching to it requires also changing the SDC. In the past, it has led to hold violations.
- We COULD route/buffer it thru the mux?
- In our signoff.sdc, or even just base_user_project_wrapper.sdc, do we need to make sure the paths through the mux and designs are constrained?
- Need to move on from gf180-rbz-fsm. It hardens, even if there are slew/fanout/cap issues. Try and tweak it later, but for now just get it in with a mux.
- Still should TRY to improve the rcp/shmul FSMs.