Skip to content

Latest commit

 

History

History
168 lines (131 loc) · 10.5 KB

0189-2023-12-11.md

File metadata and controls

168 lines (131 loc) · 10.5 KB

11 Dec 2023

Previous journal: Next journal:
0188-2023-12-10.md 0190-2024-01-17.md

GFMPW-1 finalisation

  • Reharden all: 
    make top_design_mux         &&
make top_raybox_zero_fsm    &&
make urish_simon_says       &&
make user_proj_cpu          &&
make wrapped_wb_hyperram    &&
make user_project_wrapper
    • It takes about 45 minutes for the lot on L7, 48 on L5.
    • There are (known) hold vios confined to LA-based reset lines. ./ammsum.sh reports 651 hold vios: 163 worst -0.49 on LA55 (0:trzf1), 457 worst -0.81 on LA56 (1:trzf2), 5 worst -0.38 on LA59 (4:uri).
  • Check LVS config
  • Delete junk projects from openlane/
  • Put in Anton's vgasp and solos designs, or stubs at least: Will it fix OEB vios?
  • Tidy up mux:
    • Reduce io_in counts to match the needs of each design.
      • Includes changing the simple repeater wire assignments inside the mux.
      • NOTE: It might be troublesome for designs that define all io_ins (e.g. Uri's)... because even if they're unused, will they still yield LVS errors? Hopefully less likely if
    • Change pin packing. Try to work out a grid model?? No, that seems like a bad idea.
  • Put in everyone's doco in README

Anton's extra designs

Bring in top_solo_squash and top_vga_spi_rom...

Internal/external/mux pin mapping for top_vga_spi_rom

GPIO DIR FUNCTION uo_out uio_out uio_in ui_in
8 OUT hsync 7
9 OUT vsync 3
10 OUT r0 4
11 OUT r1 0
12 OUT g0 5
13 OUT g1 1
14 OUT b0 6
15 OUT b1 2
16 OUT spi_csb 0 -
17 OUT spi_sclk 3 -
18 BIDIR spi_IO[0] 1 1
19 IN spi_in[1] - 2
20 IN spi_in[2] - 6
21 IN spi_in[3] - 7
22 IN vga_mode 0
23 IN spi_rst_mode 1
24 IN un/reg mode 2
25 IN Test_in[0] 5
26 IN Test_in[1] 6
27 IN Test_in[2] 7
28 IN (unused) -
29 IN (unused) -
30 IN (unused)
31 IN (unused)
32 IN (unused)
33 IN (unused)
34 IN (unused)
35 IN (unused)
36 OUT Test_out 4 -
37 BIDIR SPI /RST 5 5

Unused pins: ui_in[4:3]

Testing misnamed wires in UPW

Ref: Misnamed trzf2_clock_in and trzf2_reset. These are not declared anywhere. They should raise an error, because otherwise my design has no clock connected! This was discovered by looking at the GDS.

  • I'm using afmc-efabless on gf180 branch
  • I'm proving that a make user_project_wrapper works OK first: 23_12_11_15_42
  • Then I will try to change TRZF2 to use the same misnamed wires as above, and reharden UPW: 23_12_11_15_54
  • Assuming it succeeds, I will scour the run dir to look for the bad name: trzf2_clock_in -- if that doesn't find it, I will pick another more exotic PORT name, give it a bad wire, and then look for that port name in the run logs.
  • NOTE: LINTER MIGHT BE DISABLED! I didn't see any linter output. YEP, linter is disabled: "RUN_LINTER": 0 this comes from the original efabless/caravel_user_project repo at tag gfmpw-1d.
  • After scouring the logs, looking for what warning these wires hopefully produced:
    • Document where to find the warnings, and add to Tip 2312B checks
    • Try running the harden again with linting turned on, and then check for any OTHER errors too.

Here is where warnings show up about trzf2_clock_in:

$ fgrep -R trzf2_clock_in *

logs/synthesis/1-synthesis.log:/home/zerotoasic/anton/afmc-efabless/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:254: Warning: Identifier `\trzf2_clock_in' is implicitly declared.

logs/synthesis/1-synthesis.log:Warning: Wire user_project_wrapper.\trzf2_clock_in is used but has no driver.

logs/synthesis/1-synthesis.warnings:/home/zerotoasic/anton/afmc-efabless/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:254: Warning: Identifier `\trzf2_clock_in' is implicitly declared.

logs/synthesis/1-synthesis.warnings:Warning: Wire user_project_wrapper.\trzf2_clock_in is used but has no driver.

reports/synthesis/2-synthesis.chk.rpt:Warning: Wire user_project_wrapper.\trzf2_clock_in is used but has no driver.

reports/synthesis/1-synthesis.chk.rpt:Warning: Wire user_project_wrapper.\trzf2_clock_in is used but has no driver.

Updating flat gf180 branch

Try this:

  • Go into afmc-efabless
  • git remote -vv -- verify which one is efabless (let's assume: ef)
  • git fetch ef
  • git fetch github -- or whatever
  • git checkout gf180-anton34 && git pull
  • git checkout gf180 && git pull
  • Find out what git fast-forward (and --no-ff) means
  • To check what a merge from gf180-anton34 into gf180 would be like: https://www.janbasktraining.com/community/devops/is-there-a-git-merge-dry-run-option
    • I expect the biggest issue will be either the integration of submodules, including:
      • Will the flattened submodules play nice with incoming gf180-anton34, or be seen as a conflict because of the paths coexisting?
      • Will the .gitmodules file be a mess, leading to split brain?
    • Besides that, maybe some merge conflicts
  • If necessary, just start a NEW branch of efabless and repeat the flattening of submodules

TODO

  • Logo
  • Die layout graphic
  • ~~Some of Pawel's WB lines are on the fringe of being too long as antennas (several ~200%).~~ FIXED. Moved it a little closer to WB.
  • If we're having trouble with RESET hold vios, can we change its own special delay (or add one if missing), since it doesn't come directly from wb_rst_i anyway
    • We could also mess with this line, as Pawel did: 
      set_input_delay [expr $::env(CLOCK_PERIOD) * 0.35 + 1] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
      ...since it does seem extreme that the reset delay default is HALF (*0.5) a clock period...?
  • Check yesterday's TODOs.
  • Get rid of ena lines in mux.
  • Reduce total number of IOs that top_vga_spi_rom needs -- since that is my own wrapper anyway, I can delete some unused pins, e.g. even name them correctly according to their function, get rid of OEBs that are not needed, and get rid of one-sided "uio"s.
  • AFTERWARDS: Use all the links in the submitted README to see if documentation can be tidied up, e.g. to use Anton's more-detailed RBZ notes about SPI, etc.

Notes

  • NOTE: If we had to, could we use QUIT_ON_TIMING_VIOLATIONS?
  • Had to make sure that, for any IOs which have io_out connected, there was at least one corresponding case where the respective io_oeb could be pulled low to drive the output. Otherwise, the LVS check fails with an OEB error. One design was using io_in[7:6] and setting the corresponding io_oeb[7:6] both to 1 (i.e. always inputs), but it also had io_out[7:6] also driven... LVS didn't like this, so I decided to leave all io_out[7:0] disconnected completely in UPW, since none of our designs use them as outputs.
  • To make tests work we need to remove includes from these files: 
    src/rtl/debug_overlay.v
src/rtl/lzc.v
src/rtl/pov.v
src/rtl/rbzero.v
src/rtl/spi_registers.v
src/rtl/wall_tracer.v

Getting this up to efabless

  • There are still hold violations. I will try to commit and submit anyway, and get the precheck/tapeout jobs running, then try to fix (or suppress) the hold vios later. They're probably not vital... they relate to LA-based individual resets, and while they'd be nice to have, there is still the option of external reset via io_in[5] and system-wide wb_rst_i propagation.
  • To do this, I need to:
    • Flatten all of the submodules into the repo as regular directories/files, and commit them.