diff --git a/verify/uvm-python/spi_ref_model/spi_ref_model.py b/verify/uvm-python/spi_ref_model/spi_ref_model.py index c7472b5..39d8c4f 100644 --- a/verify/uvm-python/spi_ref_model/spi_ref_model.py +++ b/verify/uvm-python/spi_ref_model/spi_ref_model.py @@ -93,7 +93,10 @@ def write_bus(self, tr): # For example, to read the same resgiter uncomment the following lines data = self.regs.read_reg_value(td.addr) td = td.clone() - if td.addr in [self.regs.reg_name_to_address["ris"], self.regs.reg_name_to_address["STATUS"]]: + if td.addr in [ + self.regs.reg_name_to_address["ris"], + self.regs.reg_name_to_address["STATUS"], + ]: # pass value as it is until logic of ris is implemented pass elif td.addr == self.regs.reg_name_to_address["RXDATA"]: diff --git a/verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py b/verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py index e08f5bd..348cc56 100644 --- a/verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py +++ b/verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py @@ -29,7 +29,9 @@ async def body(self): # Add the sequqnce here # you could use method send_req to send a write or read using the register name # example for writing register by value > 5 - await self.send_req(is_write=True, reg="CTRL", data_condition=lambda data: data == 0b111) + await self.send_req( + is_write=True, reg="CTRL", data_condition=lambda data: data == 0b111 + ) for _ in range(self.num_data): # wait received fifo not empty self.clear_response_queue() diff --git a/verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py b/verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py index 5a44099..06ffdd8 100644 --- a/verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py +++ b/verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py @@ -58,7 +58,7 @@ async def body(self): ): break - cycles_additional = 8*4 + cycles_additional = 8 * 4 for _ in range(cycles_additional): await self.send_nop()