From f8eddd3439dd9712ee847d40ea614077d08f52e9 Mon Sep 17 00:00:00 2001 From: Harald Pretl Date: Wed, 28 Aug 2024 23:18:25 +0200 Subject: [PATCH] Reduce all section hierarchies by one, add titles to all callout boxes --- _sec_basic_ota.qmd | 39 +++++++++++++++++++------------------- _sec_current_mirror.qmd | 2 +- _sec_differential_pair.qmd | 4 ++-- _sec_first_steps.qmd | 22 ++++++++++----------- _sec_intro.qmd | 14 +++++++------- _sec_mosfet_diode.qmd | 32 +++++++++++++++---------------- _sec_sizing.qmd | 30 ++++++++++++++--------------- index.qmd | 30 ++++++++++++++--------------- 8 files changed, 87 insertions(+), 86 deletions(-) diff --git a/_sec_basic_ota.qmd b/_sec_basic_ota.qmd index 8df2c23d..ead468d6 100644 --- a/_sec_basic_ota.qmd +++ b/_sec_basic_ota.qmd @@ -8,7 +8,7 @@ We note that $M_{1,2}$ and $M_{3,4}$ need to be symmetric, thus will have the sa As this is an OTA the output is a current; if the load impedance is high (i.e., purely capacitive, which is often the case in integrated circuits when driving MOSFET inputs) then the voltage gain of the OTA can be high (of course, in this simple OTA it is limited). With a high-impedance loading this OTA can provide a voltage output, and this is actually how OTAs are mostly operated. -### Voltage Buffer with OTA +## Voltage Buffer with OTA In order to design an OTA we need an application, and from this we need to derive the circuit specifications. We want to use this OTA to realize a voltage buffer which lighly loads a voltage source and can drive a large capacitive load. Such a configuration is often used to, e.g., buffer a reference voltage that is needed (and thus loaded) by another circuit. The block diagram of this configuration is shown in @fig-voltage-buffer-ota. @@ -32,7 +32,7 @@ If the voltage gain of the OTA is @fig-voltage-buffer-ota is high, then $V_\math : Voltage buffer specification {#tbl-voltage-buffer-spec} -### Large-Signal Analysis of the OTA {#sec-basic-ota-large-signal} +## Large-Signal Analysis of the OTA {#sec-basic-ota-large-signal} The first step when receiving a design task is to look at the specifications, and see whether they make sense. Detailed performance of the design will be the result of the circuit simulation, but before we step into sizing we need to do a few simple calculations to (a) allows to do back-of-the-envelope gauging if the specification makes sense, and (b) the derived analytical equations will serve as guide for the sizing procedure. @@ -55,7 +55,7 @@ T_\mathrm{slew} \approx \frac{5}{2 \pi f_\mathrm{c}} = \frac{5}{2 \pi \cdot 1 \c $$ which also checks out. -### Small-Signal Analysis of the OTA {#sec-basic-ota-small-signal} +## Small-Signal Analysis of the OTA {#sec-basic-ota-small-signal} In order to size the OTA components we need to derive how MOSFET parameters define the performance. The important small-signal metrics are @@ -70,7 +70,7 @@ $$ So in order to reach an output voltage accuracy of at least 3% we need a dc gain of $A_0 > 30.2\,\text{dB}$. To allow for process and temperature variation we need to add a bit of extra gain as margin. -#### OTA Small-Signal Transfer Function +### OTA Small-Signal Transfer Function In order to derive the governing equations for the OTA we will make a few simplifications: @@ -81,7 +81,7 @@ In order to derive the governing equations for the OTA we will make a few simpli The resulting small-signal equivalent circuit is shown in @fig-basic-ota-small-signal. -::: {.callout-note} +::: {.callout-warning title="Refresh MOSFET Small-Signal Model"} Please review the MOSFET small-signal equivalent model in @fig-mosfet-small-signal-model at this point. For the PMOS just flip the model upside-down. ::: @@ -129,7 +129,7 @@ $$ s_\mathrm{zd} = -\frac{2 \gm[34]}{\Cgs[34]} $$ -#### OTA Noise +### OTA Noise For the noise analysis we ignore the pole-zero doublet due to $\Cgs[34]$ (we assume minor impact due to this) and just consider the dominant pole. For the noise analysis at the output we set the input signal to zero, and thus we arrive at the simplified small-signal circuit shown in @fig-basic-ota-small-signal-noise. @@ -140,7 +140,7 @@ $$ \overline{\Vgs[34]^2} = \frac{1}{\gm[34]^2} \left( \overline{I_\mathrm{n1}^2} + \overline{I_\mathrm{n3}^2} \right). $$ -::: {.callout-note} +::: {.callout-important title="Noise Addition"} Remember that **uncorrelated** noise quantities need to be power-summed (i.e., $I^2 = I_1^2 + I_2^2$)! ::: @@ -175,37 +175,37 @@ $$ {#eq-basic-ota-output-noise} Inspecting @eq-basic-ota-output-noise we can see that the integrated output noise is the $k T / C$ noise of the output load capacitor, enhanced by the $\gamma_{12}$ of the input differential pair, plus a (smaller) contribution of the current mirror load $M_{3,4}$. Intuitevly, this result makes sense. -::: {.callout-tip title="Exercise"} +::: {.callout-tip title="Exercise: Derivation of 5T-OTA Performance"} Please take your time and carefully go through the explanations and derivations for the 5-transistor-OTA in @sec-basic-ota-large-signal and @sec-basic-ota-small-signal. Try to do the calculations yourself; if you get stuck, review the previous chapters. ::: -### 5T-OTA Sizing +## 5T-OTA Sizing Outfitted with the governing equations derived in @sec-basic-ota-small-signal we can now size the MOSFETs in the OTA, we remember that we have to size $M_{1,2}$ and $M_{3,4}$ equally. First, we need to select a proper $\gmid$ for the MOSFET. Remembering @sec-gmid-method we see that for the input differential pair we should go for a large $\gm$, thus we select a $\gmid = 10$. As $\gds$ of $M_2$ could limit the dc gain (@eq-simple-ota-gain-dc) we go with a rather long $L = 5\,\mu\text{m}$. For current sources a small $\gmid$ is a good idea, so we start with $\gmid=5$ (because we can not go too low because of $V_\mathrm{ds,sat}$) and also an $L = 5\,\mu\text{m}$. -::: {.callout-tip title="Exercise"} +::: {.callout-tip title="Exercise: 5T-OTA Sizing"} Please size the 5T-OTA according to the previous $\gmid$ and $L$ suggestions. Please calculate the $W$ of $M_{1-6}$ and the total supply current. Please check wether gain error, total output noise, and turn-on settling is met with the calculated devices sizes and bias currents. ::: The sizing procedure and its calculation are best performed in a Jupyter notebook, as we can easily look up the exact data from the pre-computed tables: -::: {.callout-note} +::: {.callout-tip title="Solution: 5T-OTA Sizing" collapse="true"} {{< embed ./sizing/sizing_basic_ota.ipynb echo=true >}} ::: -### 5T-OTA Simulation {#sec-basic-ota-simulation} +## 5T-OTA Simulation {#sec-basic-ota-simulation} -With the initial sizing of the MOSFETs of the 5T-OTA done, we can setup a simulation testbench and check the performance parameters. +With the initial sizing of the MOSFETs of the 5T-OTA done, we can design the 5T-OTA circuit and setup a simulation testbench to check the performance parameters. -::: {.callout-tip title="Exercise"} -Please setup a testbench in Xschem for the 5T-OTA used as a voltage buffer as schown in @fig-voltage-buffer-ota. Use typical conditions for the simulation, and check how well the specification in @tbl-voltage-buffer-spec is met, and how well the derivations in @sec-basic-ota-large-signal and @sec-basic-ota-small-signal fit to the simulation results. +::: {.callout-tip title="Exercise: 5T-OTA Design and Testbench"} +Please design the circuit of the 5T-OTA. Put the OTA circuit in a separate schematic, create a symbol for it, and use this symbol in a testbench you create in Xschem for this 5T-OTA used as a voltage buffer as schown in @fig-voltage-buffer-ota. Use typical conditions for the simulation, and check how well the specification in @tbl-voltage-buffer-spec is met, and how well the derivations in @sec-basic-ota-large-signal and @sec-basic-ota-small-signal fit to the simulation results. -If you get stuck, you can find the tesbench [here](./xschem/ota-5t_tb-ac.svg) (for the small-signal analysis) and [here](./xschem/ota-5t_tb-ac.svg) (for the large-signal settling simulation). +If you get stuck, you can find the testbench and 5T-OTA schematic [here](./xschem/ota-5t_tb-ac.svg) (for the small-signal analysis) and [here](./xschem/ota-5t_tb-ac.svg) (for the large-signal settling simulation). ::: -### 5T-OTA Simulation versus PVT +## 5T-OTA Simulation versus PVT As you have seen in @sec-basic-ota-simulation running simulations by hand is tedious. When we want to check the overall performance, we have to run many simulations over various conditions: @@ -226,10 +226,11 @@ There is a CACE setup available for our 5T-OTA. The [datasheet](./cace/voltage-b After a successul run, a documentation is automatically generated. The result of a full run of this [OTA design](./xschem/ota-5t.svg) is presented here: -::: {#nte-basic-ota-cace-result .callout-note} +::: {#nte-basic-ota-cace-result .callout-note title="CACE Summary for 5T-OTA"} + {{< include ./cace/_docs/ota-5t_schematic.md >}} ::: -#### PVT Simulation Analysis +### PVT Simulation Analysis Looking at the CACE report in @nte-basic-ota-cace-result we see that (luckily) the specifiction is met for all parameters. This is great news! We now have a design that we carefully simulated across PVT and other corners, and which is ready for layout. Once we have the layout ready, we can extract the wiring parasitics ($R$ and $C$) as well as other layout-dependent effects like [well proximity](https://global.oup.com/us/companion.websites/9780195170153/pdf/proximityeffectmodels.pdf). Using this augmented netlist we can then again use CACE to check performance across conditions and parameter variations, and if we still pass all specification points then our design is finished. diff --git a/_sec_current_mirror.qmd b/_sec_current_mirror.qmd index 5bf3c4d5..6f660c49 100644 --- a/_sec_current_mirror.qmd +++ b/_sec_current_mirror.qmd @@ -15,7 +15,7 @@ For good matching in layout care has to be taken that the MOSFET widths and leng As we know from earlier investigations of the MOSFET performance in @sec-gmid-method the drain current of a MOSFET is a function of $\VGS$ and $\VDS$. As long as the MOSFET stays in saturation (i.e., $\VDS > V_\mathrm{ds,dsat}$) the drain current is just a mild function of $\VDS$ (essentially the effect of $\gds$, which is the output conductance of the MOSFET). A fundamental flaw of the basic current mirror shown in @fig-current-mirror is the mismatch of the $\VDS$ of the MOSFET. The input-side diode has $\VGS = \VDS$, whereas the output current sources have a $\VDS$ depending on the connected circuitry. Improved current mirrors exist (basically fixing this flaw), still, when just a simple current mirror is required this structure is used for its simplicity. -::: {.callout-tip title="Exercise"} +::: {.callout-tip title="Exercise: Current Mirror"} Please construct a current mirror based on the MOSFET-diode which we sized in @sec-mosfet-diode. The input current $I_\mathrm{bias} = 20\,\mu\text{A}$, and we want three output currents of size $10\,\mu\text{A}$, $20\,\mu\text{A}$, and $40\,\mu\text{A}$. Sweep the output voltage of all three current branches and see over which voltage range an acceptable current is created. For which output voltage range is the current departing from its ideal value, and why? diff --git a/_sec_differential_pair.qmd b/_sec_differential_pair.qmd index 0fd07825..b5da45b9 100644 --- a/_sec_differential_pair.qmd +++ b/_sec_differential_pair.qmd @@ -4,7 +4,7 @@ Like the current mirror in @sec-current-mirror the **differential pair** is an u In order to understand its operation it is instructive to separate the input condition into (1) a purely differential voltage, and (2) into a common-mode voltage, and see what the impact on the output currents is. -### Differential Operation of the Diffpair +## Differential Operation of the Diffpair For a differential mode of operation we assume that the input common mode voltage is constant, i.e. $V_\mathrm{in,p} + V_\mathrm{in,n} = V_\mathrm{CM}$. A differential input voltage $v_\mathrm{in}$ then results in $$ @@ -31,7 +31,7 @@ $$ {#eq-differential-pair-dm} We see in @eq-differential-pair-dm that the differential output current is simply the differential input voltage multiplied by the $\gm$ of the individual transistor. We also note that the bottom conductance $g_\mathrm{tail}$ plays no role for the small-signal differential operation. -### Common-Mode Operation of the Diffpair +## Common-Mode Operation of the Diffpair Usually, the source conductance $g_\mathrm{tail}$ is realized by a current source and ideally should be $g_\mathrm{tail} = 0$. If this is the case, then the output currents are not a function of the common-mode input voltage, and ($I_\mathrm{tail}$ is set by the tail current source) $$ diff --git a/_sec_first_steps.qmd b/_sec_first_steps.qmd index 46a0cdd6..376283dc 100644 --- a/_sec_first_steps.qmd +++ b/_sec_first_steps.qmd @@ -1,12 +1,12 @@ In this first chapter we will learn to use Xschem for schematic entry, and how to operate the ngspice SPICE simulator for circuit simulations. Further, we will make ourself familiar with the transistor and other passive components available in the IHP Microelectronics SG13G2 technology. While this is strictly speaking a BiCMOS technology offering MOSFETs as well as SiGe HBTs, we will use it as a pure CMOS technology. -### The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) {#sec-mosfet} +## The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) {#sec-mosfet} In this course, we will not dive into semiconductor physics and derive the device operation bottom-up starting from a fundamental level governed by quantum mechanics. Instead, we will treat the MOSFET as a macroscopic by assuming we have a 4-terminal device, and the performance of this device regarding its terminal voltages and currents we will largely derive from the simulation model. The circuit symbol that we will use for the n-channel MOSFET is shown in @fig-nmos-symbol, and for the p-channel MOSFET it is shown in @fig-pmos-symbol. A control voltage between gate ("G") and source ("S") causes a current to flow between drain ("D") and source. The MOSFET is a 4-terminal device, so the bulk ("B") can also control the drain-source current flow. Often, the bulk is connected to source, and then the bulk terminal is not shown to declutter the schematics. -::: {.callout-note} +::: {.callout-note title="MOSFET Background"} Strictly speaking is the drain-source current of a MOSFET controlled by the voltage between gate and bulk and the voltage between drain and source. Since bulk is often connected to source anyway, and many circuit designers historically were already familiar with the operation of the bipolar junction transistor, it is common to consider the gate-source voltage (besides the drain-source voltage) as the controlling voltage. This focus on gate-source implies that the source is special compared to the drain. In a typical physical MOSFET, however, the drain and source are constructed exactly the same, and which terminal is drain, and which terminal is source, is only determined by the applied voltage potentials, and can change dynamically during operation (think of a MOSFET operating as a switch... which side is the drain, which side is the source?). @@ -23,7 +23,7 @@ For hand calculations and theoretical discussions we will use the following simp In an ideal MOSFET no dc current is flowing into the gate, the behavior is purely capacitive. We model this by two capacitors: $\CGG = \CGS + \CGD$ is the total capacitance when looking into the gate of the MOSFET. $\CGS$ is usually the dominant capacitance, and $\CGD$ models the capacitive feedback between D and G, usually induced by a topological overlap capacitance in the physical construction of the MOSFET. This capacitance is often small compared to $\CGS$, but in situations where we have a large voltage swing at the drain this capacitance will be affected by the [Miller effect](https://en.wikipedia.org/wiki/Miller_effect). In hand calculations we will often set $\CGD = 0$. -::: {.callout-note} +::: {.callout-note title="MOSFET Bulk Terminal"} The bulk connection in @fig-mosfet-large-signal-model seems floating as we only consider it a control terminal, where the potential difference between source and bulk influences the behaviour of the MOSFET. However, we do not consider resistive or capacitive effects associated with this node, which is of course a gross simplification, but nevertheless one we will make in this course. ::: @@ -33,8 +33,8 @@ As a side note, the students who want to understand MOSFET behaviour from a phys Now, in order to get started, basic Xschem testbenches are prepared, and first simple dc sweeps of various voltages and currents will be done. But before that, please look at the import note below! -::: {.callout-important} -Throughout this material, we will stick to the following notations: +::: {.callout-important title="Mathematical Notation"} +Throughout this material, we will largely stick to the following notation: * A **dc quantity** is shown with an upper-case letter with upper-case subscripts, like $\VGS$. * Double-subscripts denote **dc sources**, like $\VDD$ and $\VSS$. @@ -43,13 +43,13 @@ Throughout this material, we will stick to the following notations: * A upper-case letter with a lower-case subscript is used to denote **RMS quantities**, like $I_\mathrm{ds}$. ::: -#### Large-Signal MOSFET Model +### Large-Signal MOSFET Model We start with an investigation into the large-signal MOSFET model shown in @fig-mosfet-large-signal-model by using the simple testbench for the LV NMOS shown in @fig-simple-nmos-tb. ![Testbench for NMOS dc sweeps.](./xschem/dc_lv_nmos.svg){#fig-simple-nmos-tb} -::: {.callout-tip title="Exercise"} +::: {.callout-tip title="Exercise: MOSFET Investigation"} Please try to execute the following steps and answer these questions: 1. Get the LV NMOS testbench (available at ) working in your IIC-OSIC-TOOLS environment. @@ -67,7 +67,7 @@ Please try to execute the following steps and answer these questions: 1. What happens when $V_\mathrm{BS} \neq 0$? ::: -#### Small-Signal MOSFET Model {#sec-mosfet-smallsignal-model} +### Small-Signal MOSFET Model {#sec-mosfet-smallsignal-model} As you have seen in the previous investigations, the large-signal model of @fig-mosfet-large-signal-model describes the behaviour of the MOSFET across a wide range of voltages applied at the MOSFET terminals. Unfortunately, for hand analysis dealing with a nonlinear model is close to impossible, at the very least it is quite tedious. @@ -83,13 +83,13 @@ $$ $$ {#eq-mosfet-noise} where $\overline{I_\mathrm{n}^2}$ is the power-spectral density of the noise in A$^2$/Hz; $k$ is the Boltzmann constant; $T$ is the absolute temperature; $\gamma$ is a parameter in simplified theory changing between $\gamma = 2/3$ in saturation and $\gamma =1$ for triode operation; $g_\mathrm{d0}$ is equal to $\gm$ in saturation and $\gds$ in triode). -::: {.callout-note} +::: {.callout-note title="MOSFET Triode and Saturation Region"} Sometimes we will refer to different operating modes of the MOSFET like "saturation" or "triode". Generally speaking, when the drain-source voltage is small, then the MOSFET acts as a resistor, and this mode of operation we call "triode" mode. When the drain-source voltage is increased, at some point the drain-source current saturates and is no longer a strong function of the drain-source voltage. This mode is called "saturation" mode. As you can see in the large-signal investigations, these transitions happen gradually, and it is difficult to define a precise point where one operating mode switches to the other one. In this sense we use terms like "triode" and "saturation" only in an approximative sense. ::: Now we need to see how the small-signal parameters seen in @fig-mosfet-small-signal-model can be investigated and estimated using circuit simulation. -::: {.callout-tip title="Exercise"} +::: {.callout-tip title="Exercise: MOSFET Small-Signal Parameters"} Please try to execute the following steps and answer the following questions: 1. Reuse the LV NMOS testbench (available at ). @@ -102,6 +102,6 @@ Please try to execute the following steps and answer the following questions: 1. What is the difference in $\gm$, $\gds$, and other parameters between the NMOS and the PMOS? Why could they be different? ::: -### Conclusion +## Conclusion Congratulations for making it thus far! By now you should have a solid grasp of the tool handling of Xschem and ngspice, and you should be familiar with the large- and small-signal operation of both NMOS and PMOS, and the parameters describing these behaviours. If you feel you are not sufficiently fluent in these things, please go back to the beginning of @sec-mosfet and revisit the relevant sections, or dive into further reading about the MOSFET operation, like in [@Chenming_Hu_2010]. diff --git a/_sec_intro.qmd b/_sec_intro.qmd index 273b352d..7110e277 100644 --- a/_sec_intro.qmd +++ b/_sec_intro.qmd @@ -4,11 +4,11 @@ The course makes heavy use of circuit simulation, using **Xschem** for schematic Tools and PDK are integrated in the **IIC-OSIC-TOOLS** Docker image, which will be used during the coursework. -::: {.callout-note} +::: {.callout-important} All course material is made publicly available on GitHub and shared under the Apache-2.0 license. ::: -### IHP's SG13G2 130nm CMOS Technology +## IHP's SG13G2 130nm CMOS Technology SG13G2 is the name of a 130nm CMOS technology (strictly speaking BiCMOS) from IHP Microelectronics. It features low-voltage (thin-oxide) core MOSFET, high-voltage (thick-oxide) I/O MOSFET, various types of linear resistors, and 7 layers of Aluminium metallization (5 thin plus 2 thick metal layers). This PDK is open-source, and the complete process specification can be found at [SG13G2 process specification](https://github.com/IHP-GmbH/IHP-Open-PDK/blob/main/ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf). While we will not do layouts in this course, the layout rules can be found at [SG13G2 layout rules](https://github.com/IHP-GmbH/IHP-Open-PDK/blob/main/ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf). @@ -24,24 +24,24 @@ For our circuit design, the most important parameters of the available devices a * **MIM capacitor**: Device `cap_cmim`; $C'=1.5\,\text{fF}/\mu\text{m}^2 \pm 10\%$, $\text{VC}_1=-26\text{ppm/V}$, $\text{TC}_1=3.6\text{ppm/K}$, breakdown voltage $>15\,\text{V}$ * **MOM capacitor**: The metal stack is well-suited for MOM capacitors due to 5 thin metal layers, but no primitive capacitor device is available at this point. -### Schematic Entry Using Xschem +## Schematic Entry Using Xschem Xschem is an open-source schematic entry tool with emphasis on integrated circuits. For up-to-date information of the many features of Xschem and the basic operation of it please look at the available [online documentation](https://xschem.sourceforge.io/stefan/xschem_man/xschem_man.html). Usage of Xschem will be learned with the first few basic examples, essentially using a single MOSFET. The usage model of Xschem is that the schematic is hierarchically drawn, and the simulation and evaluation statements are contained in the schematics. Further, Xschem offers embedded graphing, which we will mostly use. -### Circuit Simulation Using ngspice +## Circuit Simulation Using ngspice ngspice is an open-source circuit simulator with SPICE dependency [@Nagel_1975]. Besides the usual simulated types like `op` (operating point), `dc` (dc sweeps), `tran` (time-domain), or `ac` (small-signal frquency sweeps), ngspice offers a script-like control interface, where many different simulation controls and result evaluations can be done. For detailed information please refer to the latest [online manual](https://ngspice.sourceforge.io/docs/ngspice-43-manual.pdf). -### Integrated IC Design Environment (IIC-OSIC-TOOLS) +## Integrated IC Design Environment (IIC-OSIC-TOOLS) In order to make use of the various required components (tools like Xschem and ngspice, PDKs like SG13G2) easier, we will use the **IIC-OSIC-TOOLS**. This is a pre-compiled Docker image which allows to do circuit design on a virtual machine on virtually any type of computing equipment (personal PC, Raspberry Pi, cloud server) on various operating systems (Windows, macOS, Linux). For further information like installed tools, how to setup a VM, etc. please look at [IIC-OSIC-TOOLS GitHub page](https://github.com/iic-jku/IIC-OSIC-TOOLS). -::: {.callout-tip} +::: {.callout-warning title="Preparation"} Please make sure to receive information about your personal VM access ahead of the course start. ::: Experienced users can install this image on their personal computer, for JKU students the IIC will host a VM on our compute cluster and provide personal login credentials. -::: {.callout-note} +::: {.callout-warning title="Linux"} In this course, we assume that students have a basic knowledge of Linux and how to operate it using the terminal. If you are not yet familiar with Linux (which is basically a must when doing integrated circuit design as many tools are only available on Linux), then please check out a Linux introductory course or tutorial online, there are many ressources available. ::: diff --git a/_sec_mosfet_diode.qmd b/_sec_mosfet_diode.qmd index 4ee5c806..88e23269 100644 --- a/_sec_mosfet_diode.qmd +++ b/_sec_mosfet_diode.qmd @@ -6,15 +6,15 @@ Why looking at a single-transistor circuit at all? By starting with the simplest This diode is usually biased by a current source, shown as $I_\mathrm{bias}$ in the figure. Depending on MOSFET sizing with $W$ and $L$, a certain gate-source voltage $\VGS$ will develop. This voltage can be used as a biasing voltage for other circuit parts, for example. -::: {.callout-note} +::: {.callout-note title="Feedback in the MOSFET Diode"} It is important to realize that this configuration essentially employs a feedback loop for operation. The voltage at the drain of the MOSFET is sensed by the gate, and the gate voltage changes until the $I_\mathrm{D}$ is exactly equal to $I_\mathrm{bias}$. In this sense this is probably the smallest feedback circuit one can build. ::: -### MOSFET Diode Sizing +## MOSFET Diode Sizing We will now build this circuit in Xschem. For sizing the MOSFET we will use the $\gmid$ methodology introduced in @sec-gmid-method. -::: {.callout-tip title="Exercise"} +::: {.callout-tip title="Exercise: MOSFET Diode Sizing"} Please build a MOSFET diode circuit in Xschem where you use an LV NMOS, set $I_\mathrm{bias} = 20\,\mu\text{A}$, $L = 0.13\,\mu\text{m}$, and we want to use $\gmid = 10$ (often a suitable compromise between transistor speed and $\gm$ efficiency). 1. Use the figures in @sec-techsweep-nmos to find out the proper value for $W$. @@ -24,7 +24,7 @@ Please build a MOSFET diode circuit in Xschem where you use an LV NMOS, set $I_\ Before continuing, please finish the previous exercise. Once you are done, compare with the below provided solution. -::: {.callout-tip title="Solution"} +::: {.callout-tip title="Solution: MOSFET Diode Sizing" collapse="true"} 1. Using the fact that $I_\mathrm{bias} = I_\mathrm{D} = 20\,\mu\text{A}$ and $\gmid = 10$ directly provides $\gm = 0.2\,\text{mS}$. 2. Using the self-gain plot, we see that $\gm/\gds \approx 21$, so $\gds \approx 9.5\,\mu\text{S}$. The $f_\mathrm{T}$ can easily be found in the respective plot to be $f_\mathrm{T} = 23\,\text{GHz}$. 3. The $W$ of the MOSFET we find using the drain current density plot and the given bias current. Rounding to half-microns results in $W = 1\,\mu\text{m}$. @@ -34,7 +34,7 @@ Before continuing, please finish the previous exercise. Once you are done, compa An example Jupyter notebook to extract these values accurately you can find [here](./sizing/sizing_mosfet_diode.ipynb). An Xschem schematic for this exercise is provide [as well](./xschem/mosfet_diode_sizing.sch). ::: -### MOSFET Diode Large-Signal Behaviour +## MOSFET Diode Large-Signal Behaviour As discussed above, the MOSFET diode configuration is essentially a feedback loop. Before we will analyse this loop in small-signal, we want to investgate how this loop settles in the time domain, and by doing this we can observe the large-signal settling behaviour. To simulate this, we change the dc bias source from the previous example to a transient current source, which we will turn on after some ns. The resulting Xschem testbench is shown in @fig-mosfet-diode-settling-tb. @@ -44,14 +44,14 @@ In @fig-mosfet-diode-settling-tb another interesting effect can be observed: Whi It is thus generally a good idea to add power-down switches to the circuits to disable the circuit quickly by pulling floating nodes to a defined potential (usually $\VDD$ or $\VSS$) and to avoid long intermediate states during power down. This will also allow a turn-on from a well-defined off-state. -### MOSFET Diode Small-Signal Analysis +## MOSFET Diode Small-Signal Analysis We now want to investigate the small-signal behaviour of the MOSFET diode. Based on the small-signal model of the MOSFET in @fig-mosfet-small-signal-model we realize that gate and drain are shorted, and we also connect bulk to source. We can thus simplify the circit to the one shown in @fig-mosfet-diode-small-signal. {{< include figures/_fig_mosfet_diode_small_signal.qmd >}} -::: {.callout-note} -For small-signal analysis we would not need to declare one node as the ground potential. However, when doing so, and selecting the ground node strategically, we can simplify the analysis, as we usually do not formulate KCL for the ground node (as we have only $N-1$ independent KCL equations, $N$ being the number of nodes of a circuit), and the potential difference equations are simpler if one node is at $0\,V$. +::: {.callout-note title="Ground Node Selection"} +For small-signal analysis we would not need to declare one node as the ground potential. However, when doing so, and selecting the ground node strategically, we can simplify the analysis, as we usually do not formulate KCL for the ground node (as we have only $N-1$ independent KCL equations, $N$ being the number of nodes in the circuit), and the potential difference equations are simpler if one node is at $0\,V$. ::: For calculating the small-signal impedance of the MOSFET diode we formulate KCL at the top node to get @@ -66,8 +66,8 @@ $$ {#eq-mosfet-diode-impedance} When neglecting $\gds$ and at dc we get $Z_\mathrm{diode} = 1 / \gm$, which is an important result and should be memorized. -::: {.callout-important} -In circuit analysis it is often algebraically easier to work with conductances instead of impedances, so please remember that Ohm's law for a conductance is $I = G V$, and for a capacitance is $I = s C V$. When writing equations, it is also practical to keep $s C$ together, so we will strive to sort terms accordingly. +::: {.callout-important title="The Admittance is Your Friend"} +In circuit analysis it is often algebraically easier to work with admittance instead of impedance, so please remember that Ohm's law for a conductance is $I = G \cdot V$, and for a capacitance is $I = s C \cdot V$. When writing equations, it is also practical to keep $s C$ together, so we will strive to sort terms accordingly. ::: Looking at @eq-mosfet-diode-impedance we see that for low frequencies, the diode impedance is resistive, and for high frequencies it becomes capactive as the gate-source capacitance starts to dominate. The corner frequeny of this low-pass can be calculated as @@ -76,7 +76,7 @@ $$ $$ which is pretty much the transit frequency of the MOSFET! -### MOSFET Diode Stability Analysis +## MOSFET Diode Stability Analysis The diode-connected MOSFET forms a feedback loop. What is the open-loop gain? For calculating it, we are breaking the loop, and apply a dummy $\Cgs^{*}$ at the right side to keep the impedances correct. A circuit diagram is shown in @fig-mosfet-diode-openloop, we break the loop at the dotted connection. As we can see in this example, it is critically important when breaking up a loop for analysis (also for simulation!) to keep the terminal impedances the same. Only in special cases where the load impedance is very high or the driving impedance is very low is it acceptable to disregard loading effects! @@ -105,7 +105,7 @@ There is an alternative method which breaks the loop open only by adding an ac v We now want to simulate the open-loop transfer function $H_\mathrm{ol}(s)$ by using Middlebrook's method and confirm our analysis above. -::: {.callout-tip title="Exercise"} +::: {.callout-tip title="Exercise: MOSFET Diode Loop Analysis"} Please build a simulation testbench in Xschem to simulate the open-loop transfer function of the MOSFET diode. Confirm the dc gain and pole location as given by @eq-mosfet-diode-openloop-gain. If you are getting stuck you can look at this Xschem [testbench](./xschem/mosfet_diode_loopgain.sch), shown in @fig-mosfet-diode-loopgain-tb. @@ -115,7 +115,7 @@ If you are getting stuck you can look at this Xschem [testbench](./xschem/mosfet From simulation we see that the open-loop gain is $24.9\,\text{dB}$ at low frequencies, which matches quite well our prediction of $26.4\,\text{dB}$. In the Bode plot we see a low-pass with a $-3\,\text{dB}$ corner frequency of $1.4\,\text{GHz}$, which again is fairly close to our prediction of $1.1\,\text{GHz}$. -### MOSFET Diode Noise Calculation +## MOSFET Diode Noise Calculation As a final exercise on the MOSFET diode circuit we want to calculate the output noise when we consider $\VGS$ the output reference voltage which is created when passing a bias current through the MOSFET diode. The bias current we will assume noiseless. @@ -166,11 +166,11 @@ $$ {#eq-mosfet-diode-noise-rms-simplified} Inspecting @eq-mosfet-diode-noise-rms-simplified we see our familiar $kT/C$ noise enhanced by the factor $\gamma$! Calculating this value for our MOSFET diode we get $\sqrt{V_\mathrm{n,rms}^2} = \sqrt{1.38 \cdot 10^{-23} \cdot 300 \cdot 0.84 / 1.4 \cdot 10^{-15}} = 1.58\,\text{mV}$, which is a sizeable value! We run circuits in this technology at $\VDD = 1.5\,\mathrm{V}$, which leaves us with a signal swing of ca. $1.1\,\mathrm{V_{pp}}$, resulting in a dynamic range in this case of $20 \log (1.58 \cdot 10^{-3} / 0.39) \approx -48\,\text{dB}$. -::: {.callout-important} +::: {.callout-important title="Large Bandwidth and Noise"} Large BW circuits can integrate noise over a wide bandwidth resulting in considerable rms noise. ::: -::: {.callout-tip title="Exercise"} +::: {.callout-tip title="Exercise: MOSFET Diode Noise"} Please build a simulation testbench in Xschem to simulate the noise performance of the MOSFET diode, and confirm the rms noise value that we just calculated. Look at the rms value and the PSD of the noise, and play around with the integration limits. What is the effect? Can you see the flicker noise in the PSD? How much is its contribution to the rms noise? If you are getting stuck you can look at this Xschem [testbench](./xschem/mosfet_diode_noise.sch), shown in @fig-mosfet-diode-noise-tb. @@ -178,7 +178,7 @@ If you are getting stuck you can look at this Xschem [testbench](./xschem/mosfet ![Testbench for MOSFET diode noise analysis.](./xschem/mosfet_diode_noise.svg){#fig-mosfet-diode-noise-tb} ::: -### Conclusion +## Conclusion In this section we investigated the simple MOSFET-diode circuit. We learned important skills like how to derive a small-signal model, how to calculate important features like noise and open-loop gain for stability analysis. We introduced Middlebrook's method to have a mechanism to open up loops in simulation (and calculation) without disturbing operating points for change loading conditions. diff --git a/_sec_sizing.qmd b/_sec_sizing.qmd index fa92ed6e..2535bd8f 100644 --- a/_sec_sizing.qmd +++ b/_sec_sizing.qmd @@ -2,7 +2,7 @@ When designing integrated circuits it is an important question how to select var Often, transistor sizing in entry-level courses is based on the square-law model, where a simple analytical equation for the drain current can be derived. However, in nanometer CMOS, the MOSFET behaviour is much more complex than these simple models. Also, this highly simplified derivations introduce concepts like the threshold voltage or the overdrive voltage, which are interesting from a theoretical viewpoint, but bear little practical use. -::: {.callout-note} +::: {.callout-note title="MOSFET Square-Law Model"} One of the many simplifactions of the square-law model is that the mobility of the charge carriers is assumed constant (it is not). Further, the existance of a threshold voltage is assumed, but in fact this voltage is just existing given a certain definition, and depending on definition, its value changed. In addition, in nm CMOS, the threshold voltage is a function on many thing, like $W$ and $L$. ::: @@ -12,7 +12,7 @@ Being a well-established approach we select the $\gmid$ methodology introduced b The $\gmid$ methodology has the huge advantage that is catches MOSFET behavior quite accurately over a wide range of operating conditions, and the curves look very similar for pretty much all CMOS technologies, form micrometer bulk CMOS down to nanometer FinFET devices. Of course the absolute values change, but the method applies universally. -### MOSFET Characterization Testbench +## MOSFET Characterization Testbench In order to get the required tabulated data we use a testbench in Xschem which sweeps the terminal voltages, and records various large- and small-signal parameters, which are then stored in large tables. The testbench for the LV NMOS is shown in @fig-techsweep-nmos-tb, and the TB for the LV PMOS is shown in @fig-techsweep-pmos-tb. @@ -22,13 +22,13 @@ In order to get the required tabulated data we use a testbench in Xschem which s We will use Jupyter notebooks to inspect the resulting data, and interpret some important graphs. This will greatly help to understand the MOSFET behaviour. -### NMOS Characterization {#sec-techsweep-nmos} +## NMOS Characterization {#sec-techsweep-nmos} First, we will start looking at the LV NMOS. In @sec-techsweep-pmos we have the corresponding graphs for the LV PMOS. In this lecture, we will only use the LV MOSFETs. While there are also the HV types available, they are mainly used for high-voltage circuits, like circuits connecting to the outside world. Here, we only will design low-voltage circuits running at a nominal supply voltage of $1.5\,\text{V}$, so only the LV types are of interest to us. The first import graph is the plot of $\gmid$ and $f_\mathrm{T}$ versus the gate-source voltage $\VGS$. First let us answer the question why $\gmid$ is a good parameter to look at, and actually this is also the central parameter in the $\gmid$ methodology. In many circuits that are biased in class-A (i.e., with a constant quiescent current that is larger than the largest signal excursion, see [biasing](https://en.wikipedia.org/wiki/Power_amplifier_classes#Class_A)) we want to get a large amplification from a MOSFET, which corresponds to a large $\gm$. We want this by spending the minimum biasing current possible (ideally zero), as we always design for minimum power consumption. Thus, a high $\gmid$ ratio is good. -::: {.callout-note} +::: {.callout-note title="Power Consumption"} Designing for minimum power consumption is pretty much always mandated. For battery-operated equipment it is a paramount requirement, but also in other equipment electrical energy consumption is a concern, and often severly limited by the cooling capabilities of the electrical system. ::: @@ -46,8 +46,8 @@ $$ $$ {#eq-mosfet-gmid-stronginversion} with $\Vth$ the threshold voltage and $V_\mathrm{od}$ the so-called "overdrive voltage." -::: {.callout-note} -Why are we so often using $300\,\text{K}$ for a typical condition? As this corresponds to roughly $27^{\circ}\text{C}$, this accounts for some self heating compared to otherwise usual room temperatures. Further, engineers like round numbers which are easy to remember, so $300\,\text{K}$ is used as a proxy for room temperature. +::: {.callout-note title="Why 300K?"} +Why are we so often using a temperature of $300\,\text{K}$ for a typical condition? As this corresponds to roughly $27^{\circ}\text{C}$, this accounts for some self heating compared to otherwise cooler usual room temperatures. Further, engineers like round numbers which are easy to remember, so $300\,\text{K}$ is used as a proxy for room temperature. ::: As we can also see from belows plot, the peak transit frequency of the LV NMOS is about $75\,\text{GHz}$, which allows building radio-frequency circuits up to ca. $f_\mathrm{T} / 10 = 7.5\,\text{GHz}$, which is a respectible number. It is no coincidence, that the transition for RF design in the GHz-range switched from BJT-based technologies to CMOS roughly in the timeframe when 130nm CMOS became available (ca. 2000). @@ -72,12 +72,12 @@ The following plot shows the minimum drain-source voltage $V_\mathrm{ds,sat}$ th For analog circuits the noise performance is usually quite important. Thermal noise of a resistor (the Johnson-Nyquist noise) has a flat power-spectral density (PSD) given by $\overline{V_\mathrm{n}^2}/\Delta f = 4 k T R$, where $k$ is Boltzmann's constant, $T$ absolute temperature, and $R$ the value of the resistor (the unit of $\overline{V_\mathrm{n}^2}/\Delta f$ is $\text{V}^2/\text{Hz}$). This PSD is essentially flat until very high frequencies where [quantum effects](https://en.wikipedia.org/wiki/Johnson–Nyquist_noise) start to kick in. -::: {.callout-note} -We usually leave the $\Delta f$ away for a shorter notation, so we write $\overline{V_\mathrm{n}^2}$ when we actually mean $\overline{V_\mathrm{n}^2}/\Delta f$. +::: {.callout-note title="Noise Notation"} +We usually leave the $\Delta f$ away for a shorter notation, so we write $\overline{V_\mathrm{n}^2}$ when we actually mean $\overline{V_\mathrm{n}^2}/\Delta f$. In case of doubt look at the unit of a quantity, whether is shows $\text{V}^2$ or $\text{V}^2/\text{Hz}$ or $\text{V}/\sqrt{\text{Hz}}$ (or $\text{I}^2$ or $\text{I}^2/\text{Hz}$ or $\text{I}/\sqrt{\text{Hz}}$). -Please also note that the pair of $k T$ pretty much always shows up together, so when you do a calculation and you miss the one or the other, that is often a sign for miscalculation. +Please also note that the pair of $k T$ pretty much always shows up together, so when you do a calculation and you miss the one or the other, that is often a sign for miscalculation. Boltzmann's constant $k = 1.38 \cdot 10^{-23}\,\text{J/K}$ is just a scaling factor from thermal energy expressed as a temperature $T$ to energy $E = k T$ expressed in Joule. -Further, when working with PSD there is the usage of a one-sided ($f$ runs from $0$ to $\infty$) or two-sided PSD ($f$ runs from $-\infty$ to $\infty$). The default in this lecture is the usage of a **one-sided PSD**. +Further, when working with PSD there is the usage of a one-sided ($0 \ge f < \infty$) or two-sided power spectral density (PSD) ($-\infty < f < \infty$). The default in this lecture is the usage of the **one-sided PSD**. ::: In this lecture the only MOSFET noise we consider is the drain noise (as discussed in @sec-mosfet-smallsignal-model), showing up as a current noise between drain and source. For a for realistic MOSFET noise model, also a (correlated) gate noise component and the thermal noise of the gate resistance needs to be considered. @@ -88,7 +88,7 @@ The factor $\gamma$ (@eq-mosfet-noise) is a function of many things (in classica In a MOSFET, unfortunately, besides the thermal noise according to @eq-mosfet-noise, there is also a substantial low-frequency excess noise, called "flicker noise" due to its characteristic $\overline{I_\mathrm{d,nf}^2} = K_\mathrm{f}/f$ behaviour (this means that this noise PSD decreases versus frequency). In order to characterize this flicker noise the following plot shows the cross-over frequency $f_\mathrm{co}$, where the flicker noise is as large as the thermal noise. As can be seen in the below plot, this frequency is a strong function of $L$ and $\gmid$. Generally, the flicker noise is proportional to $(W L)^{-1}$, so the larger the device is, the lower the flicker noise. The parameter $\gmid$ largely stays constant when we keep $W/L$ constant, so for a given $\gmid$ flicker noise is proportinal to $1/L^2$. However, increasing $L$ lowers device speed dramatically, so here we have a trade-off between flicker-noise performance and MOSFET speed, and this can have dramatic consequences for high-speed circuits. -::: {.callout-note} +::: {.callout-note title="MOSFET Flicker Noise"} The physical origin of flicker noise is the crystal interface between silicon (Si) and the silicondioxide (SiO~2~). Since these are different materials, there are dangling bonds, which can capture charge charriers travelling in the channel. After a random time, these carriers are released, and flicker noise is the result. The amount of flicker noise is a function of the manufacturing process, and will generally be different between device types and wafer foundries. ::: @@ -96,11 +96,11 @@ As you can see in the following plot, $f_\mathrm{co}$ can reach well into the 10 {{< embed ./sizing/techsweep_sg13_plots_nmos.ipynb#fig-nmos-fco-vs-gmid-vs-l >}} -### PMOS Characterization {#sec-techsweep-pmos} +## PMOS Characterization {#sec-techsweep-pmos} In the following, we have the same plots as discussed in @sec-techsweep-nmos, but now for the PMOS. -::: {.callout-note} +::: {.callout-note title="PMOS Sign Convention"} In all PMOS plots we plot positive values for voltages and currents, to have compatible plots to the NMOS. Of course, in a PMOS, voltages and currents have different polarity compared to the NMOS. ::: @@ -114,8 +114,8 @@ $f_\mathrm{T}$ against $\gmid$ for several different $L$. One can see significan $\gm / \gds$ versus $\gmid$. Unfortunately, one can see a modelling error for the PMOS in this plot. The self gain $\gm / \gds$ reaches non-physical values, which indicates an issue with the $\gds$ modelling for the PMOS. We can not use these values for our circuit sizing, so we will use the respective NMOS plots also for the PMOS. -::: {.callout-important} -This example shows how important it is to benchmark the device models when starting to use a new technology. Modelling artifacts like the one shown are quite often happening, as setting up the device compact models and parametrizing them according to measurement data is a very complex task. In any case, just be aware that modelling issues could exist in whatever PDK you are using! +::: {.callout-important title="Beware of Modelling Issues"} +This example shows how important it is to benchmark the device models when starting to use a new technology. Modelling artifacts like the one shown are quite often happening, as setting up the device compact models and parametrizing them according to measurement data is a very complex task. In any case, just be aware that modelling issues could exist in whatever PDK you are going to use! ::: {{< embed ./sizing/techsweep_sg13_plots_pmos.ipynb#fig-pmos-gmgds-vs-gmid-vs-l >}} diff --git a/index.qmd b/index.qmd index 83fd0d27..ea893654 100644 --- a/index.qmd +++ b/index.qmd @@ -20,52 +20,52 @@ bibliography: references.bib --- {{< include _macros.qmd >}} -## Introduction {#sec-intro} +# Introduction {#sec-intro} {{< include _sec_intro.qmd >}} -## First Steps {#sec-first-steps} +# First Steps {#sec-first-steps} {{< include _sec_first_steps.qmd >}} -## Transistor Sizing Using gm/ID Methodology {#sec-gmid-method} +# Transistor Sizing Using gm/ID Methodology {#sec-gmid-method} {{< include _sec_sizing.qmd >}} -## First Circuit: MOSFET Diode {#sec-mosfet-diode} +# First Circuit: MOSFET Diode {#sec-mosfet-diode} {{< include _sec_mosfet_diode.qmd >}} -## Current Mirror {#sec-current-mirror} +# Current Mirror {#sec-current-mirror} {{< include _sec_current_mirror.qmd >}} -## Differential Pair {#sec-diff-pair} +# Differential Pair {#sec-diff-pair} {{< include _sec_differential_pair.qmd >}} -## A Basic 5-Transistor OTA {#sec-basic-ota} +# A Basic 5-Transistor OTA {#sec-basic-ota} {{< include _sec_basic_ota.qmd >}} -## Cascode Stage +# Cascode Stage -## A Fully-Differential OTA +# A Fully-Differential OTA -## Biasing the OTA +# Biasing the OTA -## An RC-OPAMP Filter +# An RC-OPAMP Filter -## Summary & Conclusion +# Summary & Conclusion -## Appendix: Middlebrook's Method {#sec-middlebrook-method} +# Appendix: Middlebrook's Method {#sec-middlebrook-method} {{< include _app_middlebrook_method.qmd >}} -## Appendix: ngspice Cheatsheet +# Appendix: ngspice Cheatsheet {{< include _app_ngspice_cheatsheet.qmd >}} -## Appendix: Xschem Cheatsheet +# Appendix: Xschem Cheatsheet {{< include _app_xschem_cheatsheet.qmd >}}