feat: update project tt_um_underserved from olofk/underserved

Commit: 7b9d08dec536623f44657c3ca316f3ce2b765910
Workflow: https://github.com/olofk/underserved/actions/runs/9323703077

projects/tt_um_underserved/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt07 f56fdf7c",
+  "app": "Tiny Tapeout tt07 11b2d371",
   "repo": "https://github.com/olofk/underserved",
-  "commit": "43b7981233d5c9bac93bc98b34033c244bcc876b",
-  "workflow_url": "https://github.com/olofk/underserved/actions/runs/9276619645",
+  "commit": "7b9d08dec536623f44657c3ca316f3ce2b765910",
+  "workflow_url": "https://github.com/olofk/underserved/actions/runs/9323703077",
   "sort_id": 1716933092204,
   "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_underserved/docs/info.md

@@ -1,11 +1,61 @@
 ## How it works
 
-Apply power. Assign inputs. Observe outputs.
+When the system boots up, it will start accessing the SPI bus to set up a connected SPI Flash memory in XIP mode and start executing instructions from there. The GPIO can be used to output data, e.g. as a bitbanged UART.
+
+![Environment](underserved_env.png)
 
 ## How to test
 
-See above.
+The testbench contains a model of an SPI Flash. A program in Verilog Hex format can be preloaded into the Flash model.
+
+Underserved can easiest be run locally using FuseSoC.
+
+Install FuseSoC
+~~~
+pip install fusesoc
+~~~
+
+Create and enter a new workspace
+~~~
+mkdir workspace && cd workspace
+~~~
+
+Register underserved as a library in the workspace
+~~~
+fusesoc library add underserved /path/to/prince
+~~~
+...if repo is available locally or...
+...to get the upstream repo
+~~~
+fusesoc library add underserved https://github.com/olofk/underserved
+~~~
+
+Show available cores in workspace (probally just underserved for now if you haven't added other libraries)
+~~~
+fusesoc core list
+~~~
+
+Show info about underserved
+~~~
+fusesoc core show underserved
+~~~
+
+Run linting (static code checks) using Verilator
+~~~
+fusesoc run --target=lint underserved
+~~~
+
+Run underserved testbench
+~~~
+fusesoc run --target=sim underserved
+~~~
+
+Run with modelsim instead of default tool (icarus)
+~~~
+fusesoc run --target=sim underserved --tool=modelsim
+~~~
+
 
 ## External hardware
 
-Yes
+Expects a compatible SPI Flash. The XIP controller was stolen from [PicoSoC](https://github.com/YosysHQ/picorv32) which also contains some info about compatible SPI Flash components.

projects/tt_um_underserved/info.yaml

@@ -32,6 +32,7 @@ project:
     - serv_1.2.1/rtl/serv_aligner.v
     - serv_1.2.1/rtl/serv_compdec.v
     - subservient_gpio.v
+    - rf_shift_reg.v
     - spimemio.v
     - underserved.v
 
@@ -48,14 +49,14 @@ pinout:
   ui[7]: ""
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
-  uo[3]: ""
-  uo[4]: "mosi"
+  uo[0]: "gpio0"
+  uo[1]: "gpio1"
+  uo[2]: "gpio2"
+  uo[3]: "gpio3"
+  uo[4]: "gpio4"
   uo[5]: "sclk"
   uo[6]: "cs_n"
-  uo[7]: "gpio"
+  uo[7]: "mosi"
 
   # Bidirectional pins
   uio[0]: ""

projects/tt_um_underserved/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_underserved,wokwi,flow completed,0h3m24s0ms,0h2m43s0ms,138992.21291450053,0.03634736,69496.10645725027,68.72,76.083,593.72,2091,0,0,0,0,0,0,0,0,0,0,-1,-1,59822,17247,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,35107278.0,0.0,50.46,58.01,4.83,15.46,-1,1647,3043,438,1812,0,0,0,1683,32,27,39,44,306,97,11,271,451,441,14,906,456,0,772,2526,4660,34255.3536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,55.080,38.870,0.3,1,10,0.72,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_underserved,wokwi,flow completed,0h3m4s0ms,0h2m23s0ms,140202.75475302746,0.03634736,70101.37737651373,68.98,77.98230000000001,619.08,2066,0,0,0,0,0,0,0,0,0,0,-1,-1,52363,16278,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,29495985.0,0.0,45.91,52.05,1.91,12.7,-1,1275,2701,330,1735,0,0,0,1437,33,20,40,40,232,91,9,153,470,466,12,841,456,1,816,2548,4662,34255.3536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,55.080,38.870,0.3,1,10,0.72,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_underserved/stats/synthesis-stats.txt

@@ -1,77 +1,80 @@
 
-81. Printing statistics.
+82. Printing statistics.
 
 === tt_um_underserved ===
 
-   Number of wires:               2075
-   Number of wire bits:           2110
-   Number of public wires:         451
-   Number of public wire bits:     486
+   Number of wires:               2050
+   Number of wire bits:           2085
+   Number of public wires:         472
+   Number of public wire bits:     507
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:               2091
-     sky130_fd_sc_hd__a2111o_2      12
-     sky130_fd_sc_hd__a2111oi_2      1
-     sky130_fd_sc_hd__a211o_2       38
-     sky130_fd_sc_hd__a211oi_2       3
-     sky130_fd_sc_hd__a21bo_2       11
-     sky130_fd_sc_hd__a21boi_2      10
-     sky130_fd_sc_hd__a21o_2        56
-     sky130_fd_sc_hd__a21oi_2       40
-     sky130_fd_sc_hd__a221o_2       28
-     sky130_fd_sc_hd__a22o_2       114
-     sky130_fd_sc_hd__a2bb2o_2       5
-     sky130_fd_sc_hd__a311o_2        1
-     sky130_fd_sc_hd__a31o_2        51
-     sky130_fd_sc_hd__a31oi_2        1
-     sky130_fd_sc_hd__a32o_2         2
-     sky130_fd_sc_hd__a41o_2         3
-     sky130_fd_sc_hd__and2_2        27
+   Number of cells:               2066
+     sky130_fd_sc_hd__a2111o_2      13
+     sky130_fd_sc_hd__a2111oi_2      2
+     sky130_fd_sc_hd__a211o_2       13
+     sky130_fd_sc_hd__a211oi_2       2
+     sky130_fd_sc_hd__a21bo_2       15
+     sky130_fd_sc_hd__a21boi_2       3
+     sky130_fd_sc_hd__a21o_2        49
+     sky130_fd_sc_hd__a21oi_2       43
+     sky130_fd_sc_hd__a221o_2       29
+     sky130_fd_sc_hd__a22o_2        44
+     sky130_fd_sc_hd__a2bb2o_2       9
+     sky130_fd_sc_hd__a311o_2        3
+     sky130_fd_sc_hd__a31o_2        19
+     sky130_fd_sc_hd__a32o_2         8
+     sky130_fd_sc_hd__a41o_2         2
+     sky130_fd_sc_hd__and2_2        40
      sky130_fd_sc_hd__and2b_2        4
-     sky130_fd_sc_hd__and3_2        65
-     sky130_fd_sc_hd__and3b_2       13
+     sky130_fd_sc_hd__and3_2        73
+     sky130_fd_sc_hd__and3b_2        6
      sky130_fd_sc_hd__and4_2        10
      sky130_fd_sc_hd__and4b_2        3
-     sky130_fd_sc_hd__and4bb_2       1
-     sky130_fd_sc_hd__buf_1        374
-     sky130_fd_sc_hd__buf_2          4
+     sky130_fd_sc_hd__and4bb_2       2
+     sky130_fd_sc_hd__buf_1        420
+     sky130_fd_sc_hd__buf_2          3
      sky130_fd_sc_hd__conb_1        16
-     sky130_fd_sc_hd__dfxtp_2      441
-     sky130_fd_sc_hd__inv_2         29
-     sky130_fd_sc_hd__mux2_2       292
+     sky130_fd_sc_hd__dfxtp_2      468
+     sky130_fd_sc_hd__inv_2         34
+     sky130_fd_sc_hd__mux2_2       379
      sky130_fd_sc_hd__mux4_2         1
-     sky130_fd_sc_hd__nand2_2      122
-     sky130_fd_sc_hd__nand3_2       12
-     sky130_fd_sc_hd__nand4_2        4
-     sky130_fd_sc_hd__nor2_2        62
-     sky130_fd_sc_hd__nor2b_2        3
-     sky130_fd_sc_hd__nor3_2         3
-     sky130_fd_sc_hd__nor3b_2        2
-     sky130_fd_sc_hd__nor4_2         1
-     sky130_fd_sc_hd__o2111a_2       2
+     sky130_fd_sc_hd__nand2_2       44
+     sky130_fd_sc_hd__nand2b_2       1
+     sky130_fd_sc_hd__nand3_2       22
+     sky130_fd_sc_hd__nand3b_2       1
+     sky130_fd_sc_hd__nand4_2        3
+     sky130_fd_sc_hd__nor2_2        55
+     sky130_fd_sc_hd__nor2b_2        1
+     sky130_fd_sc_hd__nor3_2         4
+     sky130_fd_sc_hd__nor3b_2        1
+     sky130_fd_sc_hd__nor4_2         5
+     sky130_fd_sc_hd__o2111a_2       1
      sky130_fd_sc_hd__o2111ai_2      1
-     sky130_fd_sc_hd__o211a_2       12
-     sky130_fd_sc_hd__o211ai_2       2
-     sky130_fd_sc_hd__o21a_2        26
-     sky130_fd_sc_hd__o21ai_2       14
-     sky130_fd_sc_hd__o21ba_2        2
-     sky130_fd_sc_hd__o221a_2        3
+     sky130_fd_sc_hd__o211a_2       13
+     sky130_fd_sc_hd__o211ai_2       1
+     sky130_fd_sc_hd__o21a_2        19
+     sky130_fd_sc_hd__o21ai_2       23
+     sky130_fd_sc_hd__o21ba_2        1
+     sky130_fd_sc_hd__o21bai_2       3
+     sky130_fd_sc_hd__o221a_2        2
      sky130_fd_sc_hd__o22a_2         9
-     sky130_fd_sc_hd__o22ai_2        2
-     sky130_fd_sc_hd__o2bb2a_2       7
-     sky130_fd_sc_hd__o2bb2ai_2      1
-     sky130_fd_sc_hd__o311a_2        2
+     sky130_fd_sc_hd__o2bb2a_2       4
+     sky130_fd_sc_hd__o311a_2        3
+     sky130_fd_sc_hd__o31a_2         7
      sky130_fd_sc_hd__o31ai_2        1
-     sky130_fd_sc_hd__or2_2         32
-     sky130_fd_sc_hd__or2b_2         4
-     sky130_fd_sc_hd__or3_2         16
-     sky130_fd_sc_hd__or3b_2        10
-     sky130_fd_sc_hd__or4_2         22
-     sky130_fd_sc_hd__or4b_2         9
-     sky130_fd_sc_hd__or4bb_2        3
-     sky130_fd_sc_hd__xnor2_2       30
-     sky130_fd_sc_hd__xor2_2        16
+     sky130_fd_sc_hd__o32a_2         1
+     sky130_fd_sc_hd__o32ai_2        1
+     sky130_fd_sc_hd__o41a_2         1
+     sky130_fd_sc_hd__or2_2         29
+     sky130_fd_sc_hd__or2b_2         5
+     sky130_fd_sc_hd__or3_2         20
+     sky130_fd_sc_hd__or4_2         32
+     sky130_fd_sc_hd__or4b_2         5
+     sky130_fd_sc_hd__or4bb_2        1
+     sky130_fd_sc_hd__xnor2_2       15
+     sky130_fd_sc_hd__xor2_2        18
 
-   Chip area for module '\tt_um_underserved': 22731.801600
+   Chip area for module '\tt_um_underserved': 22816.883200