feat: update project tt_um_pid_controller from Zufallsgenerat0r/PIDco…

…ntroller

Commit: f30d9f497962e0f787ea66ca0745a7d04e5f53b5
Workflow: https://github.com/Zufallsgenerat0r/PIDcontroller/actions/runs/11759271468

projects/tt_um_pid_controller/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/Zufallsgenerat0r/PIDcontroller",
-  "commit": "055540ce01693504927a2f78bf9133f4fa5ce081",
-  "workflow_url": "https://github.com/Zufallsgenerat0r/PIDcontroller/actions/runs/11745760928",
+  "commit": "f30d9f497962e0f787ea66ca0745a7d04e5f53b5",
+  "workflow_url": "https://github.com/Zufallsgenerat0r/PIDcontroller/actions/runs/11759271468",
   "sort_id": 1730891688147,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_pid_controller/info.yaml

@@ -8,7 +8,7 @@ project:
   clock_hz:     1_000_000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
   top_module:  "tt_um_pid_controller"

projects/tt_um_pid_controller/stats/synthesis-stats.txt

@@ -2,54 +2,74 @@
 
 === tt_um_pid_controller ===
 
-   Number of wires:                482
-   Number of wire bits:            517
-   Number of public wires:          33
-   Number of public wire bits:      68
+   Number of wires:               2493
+   Number of wire bits:           2528
+   Number of public wires:          64
+   Number of public wire bits:      99
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                498
-     sky130_fd_sc_hd__a2111o_2       1
-     sky130_fd_sc_hd__a211o_2        4
-     sky130_fd_sc_hd__a21bo_2        2
-     sky130_fd_sc_hd__a21boi_2       5
-     sky130_fd_sc_hd__a21o_2        31
-     sky130_fd_sc_hd__a21oi_2       24
-     sky130_fd_sc_hd__a221o_2        2
-     sky130_fd_sc_hd__a22o_2         2
-     sky130_fd_sc_hd__a2bb2o_2       1
-     sky130_fd_sc_hd__a31o_2         4
-     sky130_fd_sc_hd__a31oi_2        1
+   Number of cells:               2509
+     sky130_fd_sc_hd__a2111o_2       8
+     sky130_fd_sc_hd__a211o_2       21
+     sky130_fd_sc_hd__a211oi_2      14
+     sky130_fd_sc_hd__a21bo_2       27
+     sky130_fd_sc_hd__a21boi_2       8
+     sky130_fd_sc_hd__a21o_2        98
+     sky130_fd_sc_hd__a21oi_2      108
+     sky130_fd_sc_hd__a221o_2        3
+     sky130_fd_sc_hd__a22o_2        43
+     sky130_fd_sc_hd__a22oi_2       18
+     sky130_fd_sc_hd__a2bb2o_2      12
+     sky130_fd_sc_hd__a311o_2        4
+     sky130_fd_sc_hd__a31o_2        50
+     sky130_fd_sc_hd__a31oi_2       11
+     sky130_fd_sc_hd__a32o_2        15
      sky130_fd_sc_hd__a32oi_2        1
-     sky130_fd_sc_hd__and2_2        36
-     sky130_fd_sc_hd__and2b_2       22
-     sky130_fd_sc_hd__and3_2        14
-     sky130_fd_sc_hd__and3b_2        3
-     sky130_fd_sc_hd__and4_2         1
-     sky130_fd_sc_hd__conb_1        16
-     sky130_fd_sc_hd__dfrtp_2       33
-     sky130_fd_sc_hd__inv_2         20
-     sky130_fd_sc_hd__mux2_1         5
-     sky130_fd_sc_hd__nand2_2       23
-     sky130_fd_sc_hd__nand2b_2      12
-     sky130_fd_sc_hd__nand3_2        5
-     sky130_fd_sc_hd__nor2_2        57
-     sky130_fd_sc_hd__nor3_2         3
-     sky130_fd_sc_hd__o211a_2        1
-     sky130_fd_sc_hd__o21a_2        14
-     sky130_fd_sc_hd__o21ai_2        7
-     sky130_fd_sc_hd__o21ba_2        1
-     sky130_fd_sc_hd__o21bai_2       4
-     sky130_fd_sc_hd__o22a_2         2
-     sky130_fd_sc_hd__o2bb2a_2       1
-     sky130_fd_sc_hd__o41a_2         1
-     sky130_fd_sc_hd__or2_2         26
-     sky130_fd_sc_hd__or3_2          7
-     sky130_fd_sc_hd__or3b_2         3
-     sky130_fd_sc_hd__or4_2          1
-     sky130_fd_sc_hd__xnor2_2       66
-     sky130_fd_sc_hd__xor2_2        36
+     sky130_fd_sc_hd__and2_2       135
+     sky130_fd_sc_hd__and2b_2       72
+     sky130_fd_sc_hd__and3_2       106
+     sky130_fd_sc_hd__and3b_2        7
+     sky130_fd_sc_hd__and4_2        17
+     sky130_fd_sc_hd__and4b_2        3
+     sky130_fd_sc_hd__conb_1        17
+     sky130_fd_sc_hd__dfrtp_2       63
+     sky130_fd_sc_hd__dfstp_2        1
+     sky130_fd_sc_hd__inv_2         81
+     sky130_fd_sc_hd__mux2_1        71
+     sky130_fd_sc_hd__nand2_2      236
+     sky130_fd_sc_hd__nand2b_2      55
+     sky130_fd_sc_hd__nand3_2       36
+     sky130_fd_sc_hd__nand3b_2       4
+     sky130_fd_sc_hd__nand4_2       17
+     sky130_fd_sc_hd__nor2_2       223
+     sky130_fd_sc_hd__nor3_2        28
+     sky130_fd_sc_hd__nor3b_2        6
+     sky130_fd_sc_hd__o2111a_2       2
+     sky130_fd_sc_hd__o211a_2       18
+     sky130_fd_sc_hd__o211ai_2      13
+     sky130_fd_sc_hd__o21a_2        47
+     sky130_fd_sc_hd__o21ai_2       60
+     sky130_fd_sc_hd__o21ba_2       25
+     sky130_fd_sc_hd__o21bai_2      12
+     sky130_fd_sc_hd__o22a_2         4
+     sky130_fd_sc_hd__o22ai_2        5
+     sky130_fd_sc_hd__o2bb2a_2      14
+     sky130_fd_sc_hd__o311a_2        4
+     sky130_fd_sc_hd__o311ai_2       2
+     sky130_fd_sc_hd__o31a_2        11
+     sky130_fd_sc_hd__o31ai_2        6
+     sky130_fd_sc_hd__o32a_2         4
+     sky130_fd_sc_hd__o32ai_2        1
+     sky130_fd_sc_hd__o41a_2         2
+     sky130_fd_sc_hd__or2_2        126
+     sky130_fd_sc_hd__or3_2         48
+     sky130_fd_sc_hd__or3b_2        14
+     sky130_fd_sc_hd__or4_2         12
+     sky130_fd_sc_hd__or4b_2        10
+     sky130_fd_sc_hd__or4bb_2        2
+     sky130_fd_sc_hd__xnor2_2      321
+     sky130_fd_sc_hd__xor2_2       127
 
-   Chip area for module '\tt_um_pid_controller': 5282.566400
+   Chip area for module '\tt_um_pid_controller': 25257.974400