feat: update project tt_um_wokwi_413386991502909441 from parallellogi…

…c-/TinyTapeoutLogic2024A

Commit: 0fcb1fedaf6c05f196e4a815b11fc1bf3cf14554
Workflow: https://github.com/parallellogic-/TinyTapeoutLogic2024A/actions/runs/11763319531

projects/tt_um_wokwi_413386991502909441/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/parallellogic-/TinyTapeoutLogic2024A",
-  "commit": "f6fb257a7b1b6268bde2d8d64718e9993336aac4",
-  "workflow_url": "https://github.com/parallellogic-/TinyTapeoutLogic2024A/actions/runs/11760359569",
+  "commit": "0fcb1fedaf6c05f196e4a815b11fc1bf3cf14554",
+  "workflow_url": "https://github.com/parallellogic-/TinyTapeoutLogic2024A/actions/runs/11763319531",
   "sort_id": 1730503332763,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_wokwi_413386991502909441/info.yaml

@@ -8,7 +8,7 @@ project:
   clock_hz:     10000000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "2x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
   top_module:  "tt_um_wokwi_413386991502909441" #"tt_um_parallellogic_top"
@@ -22,14 +22,15 @@ project:
     - "charlie.v"
     - "lfsr_counter.v"
     - "priority_write.v"
+    - "signal_generator.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
   ui[0]: "CS"
   ui[1]: "SCLK"
   ui[2]: "MOSI"
-  ui[3]: "IS_RUN"
+  ui[3]: "TRIGGER"
   ui[4]: "ASIC_IN_0"
   ui[5]: "ASIC_IN_1"
   ui[6]: "ASIC_IN_2"

projects/tt_um_wokwi_413386991502909441/stats/metrics.csv

@@ -1,23 +1,23 @@
 Metric,Value
 design__lint_error__count,0
 design__lint_timing_construct__count,0
-design__lint_warning__count,1
+design__lint_warning__count,11
 design__inferred_latch__count,0
-design__instance__count,2080
-design__instance__area,16956.3
+design__instance__count,3165
+design__instance__area,22758.1
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:nom_tt_025C_1v80,17
+design__max_fanout_violation__count__corner:nom_tt_025C_1v80,21
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.0008107702014967799
-power__switching__total,0.0004175285284873098
-power__leakage__total,1.8449117789032243E-8
-power__total,0.0012283171527087688
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.02754208050693673
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.02754208050693673
-timing__hold__ws__corner:nom_tt_025C_1v80,0.33267978202768694
-timing__setup__ws__corner:nom_tt_025C_1v80,4.372335506298906
+power__internal__total,0.0008356427424587309
+power__switching__total,0.00045072208740748465
+power__leakage__total,2.5430246353153052E-8
+power__total,0.0012863902375102043
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.04506906087008847
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.04506906087008847
+timing__hold__ws__corner:nom_tt_025C_1v80,0.36093956622919066
+timing__setup__ws__corner:nom_tt_025C_1v80,4.432120573776598
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -28,13 +28,13 @@ timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
-design__max_slew_violation__count__corner:nom_ss_100C_1v60,60
-design__max_fanout_violation__count__corner:nom_ss_100C_1v60,17
+design__max_slew_violation__count__corner:nom_ss_100C_1v60,50
+design__max_fanout_violation__count__corner:nom_ss_100C_1v60,21
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
-clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.037894688459753134
-clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.037894688459753134
-timing__hold__ws__corner:nom_ss_100C_1v60,0.8962802975708652
-timing__setup__ws__corner:nom_ss_100C_1v60,3.212351364725038
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.06953360306572554
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.06953360306572554
+timing__hold__ws__corner:nom_ss_100C_1v60,0.9468610608025869
+timing__setup__ws__corner:nom_ss_100C_1v60,3.2339589699306077
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -46,12 +46,12 @@ timing__setup_vio__count__corner:nom_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,17
+design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,21
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.02140998550159711
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.02140998550159711
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.11680279296593758
-timing__setup__ws__corner:nom_ff_n40C_1v95,4.901728051084471
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.035473097685529094
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.035473097685529094
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.13440926529990066
+timing__setup__ws__corner:nom_ff_n40C_1v95,4.895203492228827
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -62,13 +62,13 @@ timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,95
-design__max_fanout_violation__count,17
+design__max_slew_violation__count,76
+design__max_fanout_violation__count,21
 design__max_cap_violation__count,0
-clock__skew__worst_hold,0.04542333304726586
-clock__skew__worst_setup,0.01886602039102278
-timing__hold__ws,0.11408985190623633
-timing__setup__ws,3.169782748221728
+clock__skew__worst_hold,-0.03092573507035872
+clock__skew__worst_setup,-0.08163470130947478
+timing__hold__ws,0.12893647625638113
+timing__setup__ws,3.173695174271158
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -79,19 +79,19 @@ timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
 timing__setup_r2r__ws,inf
 timing__setup_r2r_vio__count,0
-design__die__bbox,0.0 0.0 161.0 225.76
-design__core__bbox,2.76 2.72 158.24 223.04
+design__die__bbox,0.0 0.0 334.88 225.76
+design__core__bbox,2.76 2.72 332.12 223.04
 flow__warnings__count,1
 flow__errors__count,0
 design__io,45
-design__die__area,36347.4
-design__core__area,34255.4
-design__instance__count__stdcell,2080
-design__instance__area__stdcell,16956.3
+design__die__area,75602.5
+design__core__area,72564.6
+design__instance__count__stdcell,3165
+design__instance__area__stdcell,22758.1
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.494996
-design__instance__utilization__stdcell,0.494996
+design__instance__utilization,0.313625
+design__instance__utilization__stdcell,0.313625
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
@@ -100,48 +100,48 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,63558.9
+route__wirelength__estimated,100102
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,8
-antenna__violating__nets,5
-antenna__violating__pins,6
-route__antenna_violation__count,5
-route__net,1625
+design__instance__count__hold_buffer,3
+antenna__violating__nets,6
+antenna__violating__pins,10
+route__antenna_violation__count,6
+route__net,2129
 route__net__special,2
-route__drc_errors__iter:1,1937
-route__wirelength__iter:1,78618
-route__drc_errors__iter:2,771
-route__wirelength__iter:2,77972
-route__drc_errors__iter:3,695
-route__wirelength__iter:3,77690
-route__drc_errors__iter:4,64
-route__wirelength__iter:4,77562
-route__drc_errors__iter:5,3
-route__wirelength__iter:5,77592
+route__drc_errors__iter:1,3030
+route__wirelength__iter:1,124665
+route__drc_errors__iter:2,1442
+route__wirelength__iter:2,123911
+route__drc_errors__iter:3,1382
+route__wirelength__iter:3,123618
+route__drc_errors__iter:4,373
+route__wirelength__iter:4,123539
+route__drc_errors__iter:5,46
+route__wirelength__iter:5,123524
 route__drc_errors__iter:6,0
-route__wirelength__iter:6,77586
+route__wirelength__iter:6,123514
 route__drc_errors,0
-route__wirelength,77586
-route__vias,14773
-route__vias__singlecut,14773
+route__wirelength,123514
+route__vias,21036
+route__vias__singlecut,21036
 route__vias__multicut,0
 design__disconnected_pin__count,9
 design__critical_disconnected_pin__count,0
-route__wirelength__max,521.64
+route__wirelength__max,494.86
 timing__unannotated_net__count__corner:nom_tt_025C_1v80,27
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
 timing__unannotated_net__count__corner:nom_ss_100C_1v60,27
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
 timing__unannotated_net__count__corner:nom_ff_n40C_1v95,27
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:min_tt_025C_1v80,17
+design__max_fanout_violation__count__corner:min_tt_025C_1v80,21
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
-clock__skew__worst_hold__corner:min_tt_025C_1v80,0.02467753848893535
-clock__skew__worst_setup__corner:min_tt_025C_1v80,0.02467753848893535
-timing__hold__ws__corner:min_tt_025C_1v80,0.32797671062890915
-timing__setup__ws__corner:min_tt_025C_1v80,4.396588106913148
+clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.039329984826581496
+clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.039329984826581496
+timing__hold__ws__corner:min_tt_025C_1v80,0.35704945566318674
+timing__setup__ws__corner:min_tt_025C_1v80,4.463006091016752
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -154,13 +154,13 @@ timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__unannotated_net__count__corner:min_tt_025C_1v80,27
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
-design__max_slew_violation__count__corner:min_ss_100C_1v60,31
-design__max_fanout_violation__count__corner:min_ss_100C_1v60,17
+design__max_slew_violation__count__corner:min_ss_100C_1v60,17
+design__max_fanout_violation__count__corner:min_ss_100C_1v60,21
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
-clock__skew__worst_hold__corner:min_ss_100C_1v60,0.03347366922835834
-clock__skew__worst_setup__corner:min_ss_100C_1v60,0.03347366922835834
-timing__hold__ws__corner:min_ss_100C_1v60,0.8744468729957005
-timing__setup__ws__corner:min_ss_100C_1v60,3.255374728592096
+clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.060608519918345316
+clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.060608519918345316
+timing__hold__ws__corner:min_ss_100C_1v60,0.9279540731807968
+timing__setup__ws__corner:min_ss_100C_1v60,3.288185816700619
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -174,12 +174,12 @@ timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__unannotated_net__count__corner:min_ss_100C_1v60,27
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:min_ff_n40C_1v95,17
+design__max_fanout_violation__count__corner:min_ff_n40C_1v95,21
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.01886602039102278
-clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.01886602039102278
-timing__hold__ws__corner:min_ff_n40C_1v95,0.11408985190623633
-timing__setup__ws__corner:min_ff_n40C_1v95,4.920167523777369
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.03092573507035872
+clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.03092573507035872
+timing__hold__ws__corner:min_ff_n40C_1v95,0.12893647625638113
+timing__setup__ws__corner:min_ff_n40C_1v95,4.916810209255952
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -193,12 +193,12 @@ timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__unannotated_net__count__corner:min_ff_n40C_1v95,27
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:max_tt_025C_1v80,17
+design__max_fanout_violation__count__corner:max_tt_025C_1v80,21
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
-clock__skew__worst_hold__corner:max_tt_025C_1v80,0.032816195134580686
-clock__skew__worst_setup__corner:max_tt_025C_1v80,0.032816195134580686
-timing__hold__ws__corner:max_tt_025C_1v80,0.3388069920515801
-timing__setup__ws__corner:max_tt_025C_1v80,4.346378491249055
+clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.05441963700369005
+clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.05441963700369005
+timing__hold__ws__corner:max_tt_025C_1v80,0.364503104683265
+timing__setup__ws__corner:max_tt_025C_1v80,4.394785992848609
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -211,13 +211,13 @@ timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__unannotated_net__count__corner:max_tt_025C_1v80,27
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
-design__max_slew_violation__count__corner:max_ss_100C_1v60,95
-design__max_fanout_violation__count__corner:max_ss_100C_1v60,17
+design__max_slew_violation__count__corner:max_ss_100C_1v60,76
+design__max_fanout_violation__count__corner:max_ss_100C_1v60,21
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
-clock__skew__worst_hold__corner:max_ss_100C_1v60,0.04542333304726586
-clock__skew__worst_setup__corner:max_ss_100C_1v60,0.04542333304726586
-timing__hold__ws__corner:max_ss_100C_1v60,0.9124918856572393
-timing__setup__ws__corner:max_ss_100C_1v60,3.169782748221728
+clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.08163470130947478
+clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.08163470130947478
+timing__hold__ws__corner:max_ss_100C_1v60,0.966967200347189
+timing__setup__ws__corner:max_ss_100C_1v60,3.173695174271158
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -231,12 +231,12 @@ timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__unannotated_net__count__corner:max_ss_100C_1v60,27
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:max_ff_n40C_1v95,17
+design__max_fanout_violation__count__corner:max_ff_n40C_1v95,21
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.026117275747987802
-clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.026117275747987802
-timing__hold__ws__corner:max_ff_n40C_1v95,0.12026163738582882
-timing__setup__ws__corner:max_ff_n40C_1v95,4.88187637466431
+clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.04319611457457529
+clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.04319611457457529
+timing__hold__ws__corner:max_ff_n40C_1v95,0.1378533992642996
+timing__setup__ws__corner:max_ff_n40C_1v95,4.867205443112781
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -251,15 +251,15 @@ timing__unannotated_net__count__corner:max_ff_n40C_1v95,27
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count,27
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79993
-design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000066887
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000707723
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000101205
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000707723
+design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79994
+design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000551489
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000900303
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000544209
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000900303
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.00001020000000000000059722192469191526242866530083119869232177734375
-ir__drop__worst,0.0000668999999999999998313848781350543504231609404087066650390625
+ir__drop__avg,0.0000047500000000000002615095640035036694825976155698299407958984375
+ir__drop__worst,0.000055099999999999997612500080013120395960868336260318756103515625
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0