feat: update project tt_um_snn_with_delays_paolaunisa from PaolaUniSa…

…/tt09_chatGPT_SNN_LD

Commit: f18a95b590b6f6dd246201eaacb62f60dd6b6902
Workflow: https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11758555274

projects/tt_um_snn_with_delays_paolaunisa/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD",
-  "commit": "15b92de6f03fe496f321aa333f95ca903e5ac1e7",
-  "workflow_url": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11750648504",
+  "commit": "f18a95b590b6f6dd246201eaacb62f60dd6b6902",
+  "workflow_url": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11758555274",
   "sort_id": 1730988218526,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_snn_with_delays_paolaunisa/info.yaml

@@ -5,10 +5,10 @@ project:
   discord:      "paolaunisa"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "ChatGPT-generated Spiking Neural Network with Delays"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     5000000       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     50000000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "6x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "8x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
   top_module:  "tt_um_snn_with_delays_paolaunisa"
@@ -50,14 +50,14 @@ pinout:
   ui[7]: "input_spike[7]"
 
   # Outputs
-  uo[0]: "debug_output[0]"
-  uo[1]: "debug_output[1]"
-  uo[2]: "debug_output[2]"
-  uo[3]: "debug_output[3]"
-  uo[4]: "debug_output[4]"
-  uo[5]: "debug_output[5]"
-  uo[6]: "debug_output[6]"
-  uo[7]: "debug_output[7]"
+  uo[0]: "output[0]"
+  uo[1]: "output[1]"
+  uo[2]: "output[2]"
+  uo[3]: "output[3]"
+  uo[4]: "output[4]"
+  uo[5]: "output[5]"
+  uo[6]: "output[6]"
+  uo[7]: "output[7]"
 
   # Bidirectional pins
   uio[0]: "CS"