feat: update project tt_um_rebeccargb_colorbars from RebeccaRGB/tt-co…

…lorbars

Commit: 87cceea95d809c363551a3aeb4085f4fecafb1a8
Workflow: https://github.com/RebeccaRGB/tt-colorbars/actions/runs/11711285607

projects/tt_um_rebeccargb_colorbars/commit_id.json

@@ -1,9 +1,9 @@
 {
-  "app": "Tiny Tapeout tt09 96f3577c",
+  "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/RebeccaRGB/tt-colorbars",
-  "commit": "a7fb00abafd37deafd05f827c70b027c75b4371f",
-  "workflow_url": "https://github.com/RebeccaRGB/tt-colorbars/actions/runs/10873314401",
+  "commit": "87cceea95d809c363551a3aeb4085f4fecafb1a8",
+  "workflow_url": "https://github.com/RebeccaRGB/tt-colorbars/actions/runs/11711285607",
   "sort_id": 1727070970955,
-  "openlane_version": "OpenLane2 2.0.8",
+  "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
 }

projects/tt_um_rebeccargb_colorbars/stats/metrics.csv

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-clock__skew__worst_hold,0.004487
-clock__skew__worst_setup,0.00167
-timing__hold__ws,0.119568
-timing__setup__ws,-0.572008
+clock__skew__worst_hold,0.0013020140889526256
+clock__skew__worst_setup,0.0006808720446833694
+timing__hold__ws,0.12172893593224708
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 timing__hold__tns,0.0
-timing__setup__tns,-2.410994
-timing__hold__wns,0.0
-timing__setup__wns,-0.572008
+timing__setup__tns,-2.332527126357484
+timing__hold__wns,0
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-timing__hold_r2r__ws,0.119568
+timing__hold_r2r__ws,inf
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-timing__setup_r2r__ws,16.870649
+timing__setup_r2r__ws,inf
 timing__setup_r2r_vio__count,0
 design__die__bbox,0.0 0.0 161.0 111.52
 design__core__bbox,2.76 2.72 158.24 108.8
@@ -86,47 +86,47 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,925
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+design__instance__utilization,0.364436
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 design__power_grid_violation__count__net:VPWR,0
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 timing__drv__floating__pins,0
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-route__wirelength__estimated,12913.9
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+design__instance__count__setup_buffer,8
 design__instance__count__hold_buffer,6
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 antenna__violating__pins,0
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-route__vias,4980
-route__vias__singlecut,4980
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@@ -136,128 +136,128 @@ timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
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 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__unannotated_net__count__corner:max_ss_100C_1v60,17
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,2
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
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 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
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 timing__setup__wns__corner:max_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:max_ff_n40C_1v95,0
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 timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
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 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count__corner:max_ff_n40C_1v95,17
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-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
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 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
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+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000568003
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 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
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 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0