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feat: update project tt_um_delta_liafn from katrogacheva/tt09-LIAFN-c…
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…hip-design

Commit: e18d0342d4ea8d4828287433900c7f0a10dce44f
Workflow: https://github.com/katrogacheva/tt09-LIAFN-chip-design/actions/runs/11754494550
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 9, 2024
1 parent e6cea89 commit 62b60b8
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Showing 7 changed files with 1,356 additions and 849 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_delta_liafn/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/katrogacheva/tt09-LIAFN-chip-design",
"commit": "2b789ae1243065cddc57e665aff698e80396de40",
"workflow_url": "https://github.com/katrogacheva/tt09-LIAFN-chip-design/actions/runs/11698008837",
"commit": "e18d0342d4ea8d4828287433900c7f0a10dce44f",
"workflow_url": "https://github.com/katrogacheva/tt09-LIAFN-chip-design/actions/runs/11754494550",
"sort_id": 1730917303129,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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21 changes: 11 additions & 10 deletions projects/tt_um_delta_liafn/info.yaml
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
# Tiny Tapeout project information
project:
title: "A simple leaky integrate and fire neuron physical representation" # Project title
title: "Delta RNN and Leaky Integrate-and-Fire Nueron Circuit" # Project title
author: "Katherine Rogacheva" # Your name
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "Fires an output spike once the input has passed a certain threshold value" # One line description of what your project does
description: "A physical representation of a delta recurrent neural network (Delta RNN) and a leaky integrate-and-fire (LIF) neuron, that creates an artificial spike when the difference in the previous and current state is greater than a set delta threshold." # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)

Expand All @@ -19,6 +19,7 @@ project:
source_files:
- "tt_um_delta_liafn.v"
- "lif.v"
- "reg_state_store.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
Expand All @@ -43,14 +44,14 @@ pinout:
uo[7]: "State variable bit [7]"

# Bidirectional pins
uio[0]: ""
uio[1]: ""
uio[2]: ""
uio[3]: ""
uio[4]: ""
uio[5]: ""
uio[6]: ""
uio[7]: "Spike bit"
uio[0]: "Difference in states bit [1]"
uio[1]: "Difference in states bit [2]"
uio[2]: "Difference in states bit [3]"
uio[3]: "Difference in states bit [4]"
uio[4]: "Difference in states bit [5]"
uio[5]: "Difference in states bit [6]"
uio[6]: "Difference in states bit [7]"
uio[7]: "Difference in states bit [8]"

# Do not change!
yaml_version: 6
164 changes: 82 additions & 82 deletions projects/tt_um_delta_liafn/stats/metrics.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -3,21 +3,21 @@ design__lint_error__count,0
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Expand All @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
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Expand All @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
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Expand All @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
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Expand All @@ -86,58 +86,58 @@ flow__errors__count,0
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Expand All @@ -148,15 +148,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
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Expand All @@ -167,15 +167,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
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Expand All @@ -186,15 +186,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
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Expand All @@ -205,15 +205,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
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Expand All @@ -224,15 +224,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
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Expand All @@ -243,19 +243,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
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design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000426738
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000017588
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000426738
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79982
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000180346
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000206347
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000119393
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000206347
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.000001830000000000000054831898570195658493275914224795997142791748046875
ir__drop__worst,0.0000545000000000000033571236068841159294606768526136875152587890625
ir__drop__avg,0.000011699999999999999788190263583231853772304020822048187255859375
ir__drop__worst,0.00018000000000000001133641791550843436198192648589611053466796875
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
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