feat: update project tt_um_control_block from SiddharthN16/TT09-Contr…

…ol-Block Commit: 47ba976976c9bbee45b337ee351522458515b94b Workflow: https://github.com/SiddharthN16/TT09-Control-Block/actions/runs/11759172637
TinyTapeout · Nov 9, 2024 · 95aa2ad · 95aa2ad
1 parent bf6c633
commit 95aa2ad
Show file tree

Hide file tree

Showing 3 changed files with 95 additions and 6 deletions.
diff --git a/projects/tt_um_control_block/commit_id.json b/projects/tt_um_control_block/commit_id.json
@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/SiddharthN16/TT09-Control-Block",
-  "commit": "cacdc9a62af9b074a17927e4271a6c5c6d92c625",
-  "workflow_url": "https://github.com/SiddharthN16/TT09-Control-Block/actions/runs/11748637916",
+  "commit": "47ba976976c9bbee45b337ee351522458515b94b",
+  "workflow_url": "https://github.com/SiddharthN16/TT09-Control-Block/actions/runs/11759172637",
   "sort_id": 1731030551129,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

diff --git a/projects/tt_um_control_block/docs/info.md b/projects/tt_um_control_block/docs/info.md
@@ -9,10 +9,99 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Control block for a basic 8-bit CPU design building off the SAP-1.
+This project implements the control block of an 8-bit CPU design building off the SAP-1.
 
-Implemented using a 6 stage sequential counter for sequencing micro-instructions, and a LUT for corresponding op-code to operation(s).
+The control block is implemented using a 6 stage sequential counter for sequencing micro-instructions, and a LUT for corresponding op-code to operation(s).
 
-## How to test
+## Supported Instructions
+
+| **Mnemonic**  | **Opcode** | **Function**                                             |
+| ------------- | ---------- | -------------------------------------------------------- |
+| HLT           | 0x0        | Stop processing                                          |
+| NOP           | 0x1        | No operation                                             |
+| ADD {address} | 0x2        | Add B register to A register, leaving result in A        |
+| SUB {address} | 0x3        | Subtract B register from A register, leaving result in A |
+| LDA {address} | 0x4        | Put RAM data at {address} into A register                |
+| OUT           | 0x5        | Put A register data into Output register and display     |
+| STA {address} | 0x6        | Store A register data in RAM at {address}                |
+| JMP {address} | 0x7        | Change PC to {address}                                   |
+
+### Instruction Notes
+
+- All instructions consist of an opcode (most significant 4 bits), and an address (least significant 4 bits, where applicable)
+
+## Control Signal Descriptions
+
+| **Control Signal** | **Array** | **Component**    | **Function**                                        |
+| ------------------ | --------- | ---------------- | --------------------------------------------------- |
+| CP                 | 14        | PC               | Increments the PC by 1                              |
+| EP                 | 13        | PC               | Enable signal for PC to drive the bus               |
+| LP                 | 12        | PC               | Tells PC to load value from the bus                 |
+| nLma               | 11        | MAR              | Tells MAR when to load address from the bus         |
+| nLmd               | 10        | MAR              | Tells MAR when to load memory from the bus          |
+| nCE                | 9         | RAM              | Enable signal for RAM to drive the bus              |
+| nLr                | 8         | RAM              | Tells RAM when to load memory from the MAR          |
+| nLi                | 7         | IR               | Tells IR when to load instruction from the bus      |
+| nEi                | 6         | IR               | Enable signal for IR to drive the bus               |
+| nLa                | 5         | A Reg            | Tells A register to load data from the bus          |
+| Ea                 | 4         | A Reg            | Enable signal for A register to drive the bus       |
+| Su                 | 3         | ALU              | Activate subtractor instead of adder                |
+| Eu                 | 2         | ALU              | Enable signal for Adder/Subtractor to drive the bus |
+| nLb                | 1         | B Reg            | Tells B register to load data from the bus          |
+| nLo                | 0         | Output Reg       | Tells Output register to load data from the bus     |
+
+## Sequencing Details
+
+- The control sequencer is negative edge triggered, so that control signals can be steady for the next positive clock edge, where the actions are executed.
+- In each clock cycle, there can only be one source of data for the bus, however any number components can read from the bus.
+- Before each run, a CLR signal is sent to the PC and the IR.
+
+## Instruction Micro-Operations
 
-Provide input of opcode. Check that the correct output bits are being asserted/deasserted properly.
+| Stage  | **HLT**  | **NOP**  | **STA**   | **JMP**  |
+| ------ | -------- | -------- | --------- | -------- |
+| **T0** | Ep, nLma | Ep, nLma | Ep, nLma  | Ep, nLma |
+| **T1** | Cp       | Cp       | Cp        | Cp       |
+| **T2** | nCE, nLi | nCE, nLi | nCE, nLi  | nCE, nLi |
+| **T3** | \*\*     | \-       | nEi, nLma | nEi, Lp  |
+| **T4** |          | \-       | Ea, nLmd  | \-       |
+| **T5** |          | \-       | nLr       | \-       |
+
+| Stage  | **LDA**   | **ADD**   | **SUB**     | **OUT**  |
+| ------ | --------- | --------- | ----------- | -------- |
+| **T0** | Ep, nLma  | Ep, nLma  | Ep, nLma    | Ep, nLma |
+| **T1** | Cp        | Cp        | Cp          | Cp       |
+| **T2** | nCE, nLi  | nCE, nLi  | nCE, nLi    | nCE, nLi |
+| **T3** | nEi, nLma | nEi, nLma | nEi, nLma   | Ea, nLo  |
+| **T4** | nCE, nLa  | nCE, nLb  | nCE, nLb    | \-       |
+| **T5** | \-        | Eu, nLa   | Su, Eu, nLa | \-       |
+
+### Instruction Micro-Operations Notes
+
+- First three micro-operations are common to all instructions.  
+- NOP instruction executes only the first three micro-operations.
+- HLT instruction transitions to a holding stage after T3, preventing the system for continuing
+
+## IO Table
+
+| **Name**      | **Description**                     | **I/O** | **Width** | **Trigger**     |
+| ------------- | ----------------------------------- | ------- | --------- | --------------- |
+| clk           | Clock signal                        | I       | 1         | Edge Transition |
+| rst_n         | Set stage to 0                      | I       | 1         | Active Low      |
+| ui_in[3:0]    | Opcode                              | I       | 4         | NA              |
+| uo_out[7]     | If 1, the system is halted          | O       | 1         | Active High     |
+| uo_out[6:0]   | control_signals[14:8]               | O       | 7         | NA              |
+| uio_out[7:0]  | control_signals[7:0]                | O       | 8         | NA              |
+| ui_oe[7:0]    | All Bidirectional pins are outputs  | O       | 8         | NA              |
+| uio_in[7:0]   | Unused                              | I       | 8         | NA              |
+| ena           | Unused                              | I       | 1         | Active High     |
+
+### IO Table Notes
+- See [Control Signal Descriptions](#control-signal-descriptions) for the list of output control signals, and their correspondance in the control_signal vector
+
+## How to test
+The control block can be tested by:
+- Providing an opcode through the `ui_in[3:0]` input pins.
+- Monitoring the `uo_out[7:0]` and `uio_out[7:0]` output pins for the control signals and halt status
+- For a given opcode, follow its [Instruction Micro-Operation](#instruction-micro-operations) table to validate the control signal sequences
+- Consider using a logic analyzer to generate a waveform and analyze the stages, or slow down the clock to manually observe the control signals at various times
diff --git a/projects/tt_um_control_block/tt_um_control_block.gds b/projects/tt_um_control_block/tt_um_control_block.gds