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Pull requests: Xilinx/llvm-aie
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[AIE2P] Fix EX registers' Calling Convention to follow AIE ABI
#300
opened Jan 22, 2025 by
khallouh
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Update download and upload artifacts actions to v4 ahead of deprecation
#295
opened Jan 21, 2025 by
philippjh
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[AIE2P] !Fixup Combine G_SHUFFLE_VECTOR into G_AIE_VSEL
#294
opened Jan 21, 2025 by
katerynamuts
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[AIE2P] Combine G_SHUFFLE_VECTOR into Extract+Broadcast
#284
opened Jan 20, 2025 by
katerynamuts
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[AIE2P] Enable legalization of 4x128-bit G_CONCAT_VECTORS
#283
opened Jan 17, 2025 by
konstantinschwarz
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[AIE2P] Legalization and instruction selection support for G_FADD/G_FSUB
#274
opened Jan 16, 2025 by
katerynamuts
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[AIE] Solve it. Work In Progress adding a solver-based postpipeliner
#255
opened Jan 10, 2025 by
martien-de-jong
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Draft
[AIE NFC] Postpipeliner cleanups and refactorings
#253
opened Jan 8, 2025 by
martien-de-jong
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[AIEX] Schedule SWP epilogue with "free" instructions
#247
opened Dec 10, 2024 by
andcarminati
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Add support for bfloat in VInsert PreLegalizerCombiner
#243
opened Nov 21, 2024 by
abhinay-anubola
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Support for allowing direct VEXTRACT to 20-bit registers
#233
opened Nov 8, 2024 by
abhinay-anubola
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[AIEX] Ignore bank conflict if in the next cycle we cannot schedule the instruction.
#229
opened Nov 1, 2024 by
krishnamtibrewala
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Draft
[GlobalISel] Match G_SHUFFLE_VECTORs representing sub-vector extracts
#224
opened Oct 25, 2024 by
konstantinschwarz
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Draft
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