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0178-2023-11-28.md

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28 Nov 2023

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GFMPW-1 attempt at raybox-zero

Yesterday I got a successful harden with solo_squash, and got the precheck to pass.

I then managed to get it to pass precheck and tapeout on Efabless for GFMPW-1. That was just a test, so I've since removed it from the shuttle.

Let's see if we can do it again now for the version of raybox-zero that went to EW's chipIgnite.

  1. # NOTE: For me, ~/CUP symlinks to ~/asic_tools/caravel_user_project
# which symlinks to ~/anton/<whatever_cup_project_name>
cd ~/anton
git clone -b gfmpw-1c https://github.com/efabless/caravel_user_project.git algofoogle-multi-caravel
cd algofoogle-multi-caravel
git switch -c main-gf180  # What we'll call our default branch for this GFMPW-1 submission
rm ~/asic_tools/caravel_user_project
ln -s ~/anton/algofoogle-multi-caravel ~/asic_tools/caravel_user_project
cd ~/CUP
  2. Create algofoogle-multi-caravel GitHub repo, and add it as a remote, then push: 
    git remote add github [email protected]:algofoogle/algofoogle-multi-caravel
git push -u github main-gf180
  3. Set env vars for GF180: 
    #NOTE: Already set for me:
# OPENLANE_ROOT=/home/zerotoasic/asic_tools/openlane
# PDK_ROOT=/home/zerotoasic/asic_tools/pdk
export PDK=gf180mcuD
  4. Now at this point I could run make setup but that would use up an extra couple of GB, so instead I'll move the following into this tree from my last run: 
    mv ~/anton/solo-squash-caravel-v2/caravel .
mv ~/anton/solo-squash-caravel-v2/dependencies .
mv ~/anton/solo-squash-caravel-v2/mgmt_core_wrapper .
  5. Also: 
    mkdir JUNK
ls -1d JUNK caravel dependencies mgmt_core_wrapper >> .gitignore
  6. Do a test harden as-is with example project: 
    time make user_proj_example
# 8 linter warnings, some fanouts, and it takes about 06:40s
    ...and then try in the UPW: 
    time make user_project_wrapper
# Takes about 05:40s
  7. Remove example files that we don't care about (influenced by this automated cleanup stuff): 
    git rm -rf gds verilog/gl mag maglef def lef lib sdc spef spi signoff verilog/rtl/user_proj_example.v
rm -rf sdf gds verilog/gl mag maglef def lef lib sdc spef spi signoff
rm -rf openlane/user_proj_example/runs openlane/user_project_wrapper/runs
  8. Commit this 'tidy' version: 
    git commit -am "Removed (most) example stuff"
git push
  9. Now let's integrate raybox-zero...
  10. NOTE: For now we'll bring in raybox-zero as a git submodule (but when ready to push to Efabless, we'll end up just collapsing the submodules to local directories): 
    git submodule add -b ew [email protected]:algofoogle/raybox-zero verilog/rtl/raybox-zero
    Actually let's make some minor tweaks in its own gf180 branch: 
    git checkout -b gf180
    I then commented out timescales and made a new commit.
  11. Edit verilog/includes/* files to replace user_proj_example with appropriate files (NOTE: 1 file for GLs, all raybox source files for RTL).
  12. Put the instantiation snippet in verilog/rtl/user_project_wrapper.v and adapt if needed (e.g. to use extra IOs). One change needed is the power pin names; we want this: 
    `ifdef USE_POWER_PINS
    .vdd(vdd),	// User area 1 1.8V power
    .vss(vss),	// User area 1 digital ground
`endif
    ...and we do NOT want this: 
    `ifdef USE_POWER_PINS
    .vccd1(vccd1),        // User area 1 1.8V power
    .vssd1(vssd1),        // User area 1 digital ground
`endif
  13. Update verilog/rtl/user_defines.v accordingly.
  14. Create openlane/top_ew_algofoogle/config.json and, if desired, pin_order.cfg (and reference it in config.json)
  15. Edit openlane/user_project_wrapper/config.json and macro.cfg
  16. Add to repo: 
    git add openlane/top_ew_algofoogle
git commit -am "First attempt at integrating raybox-zero"
git push

First attempt at hardening raybox-zero with GF180

cd ~/CUP
git pull
git submodule init
git submodule update
make top_ew_algofoogle

With FP_CORE_UTIL set to 35, floorplan in GF180 comes out to about 955x953µm. It fails with setup violations at the typical corner (I think 17.23ns over in the worst case).

We might be able to improve this if we can:

  • fix SDC file;
  • get a more-dense layout;
  • change pin ordering;
  • add extra slack margins;
  • drop to Q10.10;
  • work with a halved clock (halved resolution);
  • change multipliers and reciprocal in FSM to be more incremental.

Final steps for a GFMPW-1 submission

  • Change name of top module to include ...raybox_zero...
  • Improve LA use and expand IOs
  • Remove 'reset lock' logic
  • Decide on clock source
  • Better doco
  • Photos/screenshots
  • Testing evidence
  • Banner image