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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.1k 613

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.3k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.4k 220

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 334

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 837 222

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 735 177

Repositories

Showing 10 of 110 repositories
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 129 Apache-2.0 23 17 24 Updated Jan 22, 2025
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 258 Apache-2.0 76 20 15 Updated Jan 22, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 13 Apache-2.0 2 8 1 Updated Jan 22, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 99 Apache-2.0 47 111 62 Updated Jan 22, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,103 Apache-2.0 613 314 (1 issue needs help) 172 Updated Jan 22, 2025
  • firrtl-spec Public

    The specification for the FIRRTL language

    chipsalliance/firrtl-spec’s past year of commit activity
    TeX 49 28 25 16 Updated Jan 22, 2025
  • chipsalliance/veer-el2-dashboard’s past year of commit activity
    HTML 0 1 0 0 Updated Jan 22, 2025
  • rocket-pcb Public

    PCB libraries and templates for rocket-chip based FPGA/ASIC designs

    chipsalliance/rocket-pcb’s past year of commit activity
    Verilog 7 Apache-2.0 2 0 1 Updated Jan 22, 2025
  • rocket-pcblib Public
    chipsalliance/rocket-pcblib’s past year of commit activity
    1 Apache-2.0 0 0 0 Updated Jan 22, 2025
  • synlig Public

    SystemVerilog synthesis tool

    chipsalliance/synlig’s past year of commit activity
    Verilog 176 Apache-2.0 23 69 10 Updated Jan 22, 2025