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Merge branch 'main' of github.com:efabless/EF_SPI
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@NouranAbdelaziz
NouranAbdelaziz committed Jan 8, 2025
2 parents 870d558 + e10fbfb commit b3c5ebc
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24 changes: 21 additions & 3 deletions EF_SPI.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ info:
license: APACHE 2.0
author: Mohamed Shalan
email: [email protected]
version: v1.0.10
version: v1.0.11
date: 17-09-2024
category: digital
tags:
Expand Down Expand Up @@ -137,14 +137,22 @@ ports:
width: 1
direction: input
description: enable for spi master pulse generation
- name: done
width: 1
direction: output
description: spi done flag.
- name: busy
width: 1
direction: output
description: spi busy flag.

external_interface:
- name: miso
port: miso
width: 1
direction: input
description: SPI Master In Slave Out.
sync: True
sync: False
- name: mosi
port: mosi
width: 1
Expand Down Expand Up @@ -236,7 +244,7 @@ registers:
write_port: clk_divider
description: SPI clock Prescaler; should have a value >= 2. SPI Clock Frequency = System Clock / PR.
- name: STATUS
size: 6
size: 8
mode: r
fifo: no
offset: 20
Expand Down Expand Up @@ -274,6 +282,16 @@ registers:
bit_width: 1
read_port: rx_level_above
description: Receive FIFO level is Above Threshold.
- name : busy
bit_offset: 6
bit_width: 1
read_port: busy
description: spi busy flag.
- name : done
bit_offset: 7
bit_width: 1
read_port: done
description: spi done flag.


flags:
Expand Down
7 changes: 2 additions & 5 deletions hdl/rtl/EF_SPI.v
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Expand Up @@ -49,8 +49,8 @@ module EF_SPI #(parameter
output wire tx_level_below,
output wire [FAW-1:0] tx_level,

//output busy,
//output done,
output wire busy,
output wire done,

input wire miso,
output wire mosi,
Expand All @@ -61,9 +61,6 @@ module EF_SPI #(parameter

localparam FDW = 8;

wire busy;
wire done;

// TX Side
wire tx_wr = wr;
wire tx_rd = !tx_empty & !busy;
Expand Down
34 changes: 32 additions & 2 deletions hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,10 @@ module EF_SPI_AHBL #(
CDW = 8,
FAW = 4
) (




input wire HCLK,
input wire HRESETn,
input wire HWRITE,
Expand Down Expand Up @@ -138,7 +142,21 @@ module EF_SPI_AHBL #(
localparam MIS_REG_OFFSET = 16'hFF04;
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;
wire clk = HCLK;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(HCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = HRESETn;


Expand Down Expand Up @@ -182,6 +200,8 @@ module EF_SPI_AHBL #(
wire [FAW-1:0] tx_level;
wire [1-1:0] ss;
wire [1-1:0] enable;
wire [1-1:0] done;
wire [1-1:0] busy;

// Register Definitions
wire [8-1:0] RXDATA_WIRE;
Expand Down Expand Up @@ -209,13 +229,15 @@ module EF_SPI_AHBL #(
else if(ahbl_we & (last_HADDR[16-1:0]==PR_REG_OFFSET))
PR_REG <= HWDATA[CDW-1:0];

wire [6-1:0] STATUS_WIRE;
wire [8-1:0] STATUS_WIRE;
assign STATUS_WIRE[0 : 0] = tx_empty;
assign STATUS_WIRE[1 : 1] = tx_full;
assign STATUS_WIRE[2 : 2] = rx_empty;
assign STATUS_WIRE[3 : 3] = rx_full;
assign STATUS_WIRE[4 : 4] = tx_level_below;
assign STATUS_WIRE[5 : 5] = rx_level_above;
assign STATUS_WIRE[6 : 6] = busy;
assign STATUS_WIRE[7 : 7] = done;

wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
Expand Down Expand Up @@ -251,6 +273,11 @@ module EF_SPI_AHBL #(
else
TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;

localparam GCLK_REG_OFFSET = 16'hFF10;
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0;
else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET))
GCLK_REG <= HWDATA[1-1:0];

reg [5:0] IM_REG;
reg [5:0] IC_REG;
reg [5:0] RIS_REG;
Expand Down Expand Up @@ -324,6 +351,8 @@ module EF_SPI_AHBL #(
.tx_level(tx_level),
.ss(ss),
.enable(enable),
.done(done),
.busy(busy),
.miso(miso),
.mosi(mosi),
.csb(csb),
Expand All @@ -347,6 +376,7 @@ module EF_SPI_AHBL #(
(last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
(last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
(last_HADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG :
(last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;

assign HREADYOUT = 1'b1;
Expand Down
32 changes: 30 additions & 2 deletions hdl/rtl/bus_wrappers/EF_SPI_AHBL.v
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,10 @@ module EF_SPI_AHBL #(
CDW = 8,
FAW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif
`AHBL_SLAVE_PORTS,
input wire [1-1:0] miso,
output wire [1-1:0] mosi,
Expand All @@ -54,7 +58,21 @@ module EF_SPI_AHBL #(
localparam MIS_REG_OFFSET = `AHBL_AW'hFF04;
localparam RIS_REG_OFFSET = `AHBL_AW'hFF08;
localparam IC_REG_OFFSET = `AHBL_AW'hFF0C;
wire clk = HCLK;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk(HCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = HRESETn;


Expand Down Expand Up @@ -82,6 +100,8 @@ module EF_SPI_AHBL #(
wire [FAW-1:0] tx_level;
wire [1-1:0] ss;
wire [1-1:0] enable;
wire [1-1:0] done;
wire [1-1:0] busy;

// Register Definitions
wire [8-1:0] RXDATA_WIRE;
Expand All @@ -103,13 +123,15 @@ module EF_SPI_AHBL #(
assign clk_divider = PR_REG;
`AHBL_REG(PR_REG, 'h2, CDW)

wire [6-1:0] STATUS_WIRE;
wire [8-1:0] STATUS_WIRE;
assign STATUS_WIRE[0 : 0] = tx_empty;
assign STATUS_WIRE[1 : 1] = tx_full;
assign STATUS_WIRE[2 : 2] = rx_empty;
assign STATUS_WIRE[3 : 3] = rx_full;
assign STATUS_WIRE[4 : 4] = tx_level_below;
assign STATUS_WIRE[5 : 5] = rx_level_above;
assign STATUS_WIRE[6 : 6] = busy;
assign STATUS_WIRE[7 : 7] = done;

wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
Expand All @@ -133,6 +155,9 @@ module EF_SPI_AHBL #(
assign tx_flush = TX_FIFO_FLUSH_REG[0 : 0];
`AHBL_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)

localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10;
`AHBL_REG(GCLK_REG, 0, 1)

reg [5:0] IM_REG;
reg [5:0] IC_REG;
reg [5:0] RIS_REG;
Expand Down Expand Up @@ -201,6 +226,8 @@ module EF_SPI_AHBL #(
.tx_level(tx_level),
.ss(ss),
.enable(enable),
.done(done),
.busy(busy),
.miso(miso),
.mosi(mosi),
.csb(csb),
Expand All @@ -224,6 +251,7 @@ module EF_SPI_AHBL #(
(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
(last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;

assign HREADYOUT = 1'b1;
Expand Down
64 changes: 26 additions & 38 deletions hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -102,10 +102,10 @@ module EF_SPI_APB #(
CDW = 8,
FAW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif




input wire PCLK,
input wire PRESETn,
input wire PWRITE,
Expand Down Expand Up @@ -140,27 +140,20 @@ module EF_SPI_APB #(
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];

`ifdef FPGA
wire clk = PCLK;
`else
(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
`endif
.GCLK(clk_g),
.GATE(clk_gated_en),
.CLK(PCLK)
);

wire clk = clk_g;
`endif
reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(PCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = PRESETn;


Expand Down Expand Up @@ -190,6 +183,8 @@ module EF_SPI_APB #(
wire [FAW-1:0] tx_level;
wire [1-1:0] ss;
wire [1-1:0] enable;
wire [1-1:0] done;
wire [1-1:0] busy;

// Register Definitions
wire [8-1:0] RXDATA_WIRE;
Expand Down Expand Up @@ -217,13 +212,15 @@ module EF_SPI_APB #(
else if(apb_we & (PADDR[16-1:0]==PR_REG_OFFSET))
PR_REG <= PWDATA[CDW-1:0];

wire [6-1:0] STATUS_WIRE;
wire [8-1:0] STATUS_WIRE;
assign STATUS_WIRE[0 : 0] = tx_empty;
assign STATUS_WIRE[1 : 1] = tx_full;
assign STATUS_WIRE[2 : 2] = rx_empty;
assign STATUS_WIRE[3 : 3] = rx_full;
assign STATUS_WIRE[4 : 4] = tx_level_below;
assign STATUS_WIRE[5 : 5] = rx_level_above;
assign STATUS_WIRE[6 : 6] = busy;
assign STATUS_WIRE[7 : 7] = done;

wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
Expand Down Expand Up @@ -310,17 +307,6 @@ module EF_SPI_APB #(

assign IRQ = |MIS_REG;

reg [0:0] _miso_reg_[1:0];
wire _miso_w_ = _miso_reg_[1];
always@(posedge PCLK or negedge PRESETn)
if(PRESETn == 0) begin
_miso_reg_[0] <= 'b0;
_miso_reg_[1] <= 'b0;
end
else begin
_miso_reg_[0] <= miso;
_miso_reg_[1] <= _miso_reg_[0];
end
EF_SPI #(
.CDW(CDW),
.FAW(FAW)
Expand Down Expand Up @@ -349,7 +335,9 @@ module EF_SPI_APB #(
.tx_level(tx_level),
.ss(ss),
.enable(enable),
.miso(_miso_w_),
.done(done),
.busy(busy),
.miso(miso),
.mosi(mosi),
.csb(csb),
.sclk(sclk)
Expand Down
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