Rev 1.0 update #9
Conversation
## Schematic Part number updates - R41 changed from "RC0201FR-0778R7L" to "RMCF0201FT78K7" - R71, R72 changed from "RC0201JR-071ML" to "RC0201JR-075M1L" - U10, U13 alternate PN "NCP339BFCT2G" added ## PCB Design Rule Constraints - Copper Minimum clearance changed from 0 to 3 mils - Minimum thermal relief spoke count changed from 2 to 1 - Solder mask aperture bridges items with different nets changed from Error to Warning - Silkscreen Minimum text height changed from 0.8mm to 0.5mm Cleaned up unconnected ends. Removed PMIC_ON_REQ via connected on only one layer. Removed redundant co-located drilled holes. Silkscreen logo updated
R2 and R3 pulldown resistors moved to make space. U13 and J3 nudged as well.
Fixed schematic unit number issue and re-linked to PCB. New gerbers, STEP file, schematic PDF. Deleted old KiCAD 6 files.
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Looks good, thanks for the updates. Lots of new DRC problems but it appears to be all false positives introduced in the transition for version 8. Could you double check or update the settings for solder mask settings with the board house? |
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The manufacturer wants a minimum web clearance of 3.5 mil and solder mask expansion of 2 mil. This leaves a ton of solder mask aperture bridges. I sent them an email to ask if they could handle a tighter clearance. Is some amount of solder mask aperture bridges acceptable? |
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The mask bridges would make the boards harder to solder reliably. I didn't have a problem with the layout in the initial prototypes through pcbway, whose clearance sounds about the same, and I'm not sure who made the second round. We're not going to re-layout the board, but I would like a clean DRC so we're not obscuring real issues. I guess it's up to the board house if they think they can make these. |
Reduced solder mask expansion to 1 mil and minimum web width to 6 mil.
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They allowed me to bring the solder mask expansion down to 1 mil with 3 mil web width. That cleared out the errors. All that's left in the DRC is silkscreen clipping and the footprints not matching the library warnings. Just pushed a new commit with the changes. |
Exported new production files, updated rev number and dates on schematic and PCB.
pwr label was still at the old button location. Moved it across to the new location. Updated front silkscreen gerber layer.
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pwr button label was in the wrong place. Just pushed another update to fix. |
Moved btn0 and btn1 to allow for v-score panel.
Updated to KiCAD 8.
Generated new gerbers, BOM, and STEP files.