First draft of section "Intro" and "First Steps" finished

.gitignore

@@ -11,3 +11,5 @@
 /xschem/simulation
 /_sec_intro_files
 /_sec_sizing_files
+/figures/_fig_mosfet_diode_files
+/figures/_fig_mosfet_small_signal_model_files

LICENSE

@@ -186,7 +186,8 @@
       same "printed page" as the copyright notice for easier
       identification within third-party archives.
 
-   Copyright [yyyy] [name of copyright owner]
+   Copyright 2024 Harald Pretl and colleagues, Johannes Kepler University,
+   Linz, Austria
 
    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.

_sec_intro.qmd

@@ -4,11 +4,13 @@ The course makes heavy use of circuit simulation, using **Xschem** for schematic
 
 Tools and PDK are integrated in the **IIC-OSIC-TOOLS** Docker image, which will be used during the coursework.
 
-All course material is made publicly available and shared under the Apache-2.0 license.
+::: {.callout-note}
+All course material is made publicly available on GitHub and shared under the Apache-2.0 license.
+:::
 
 ### IHP's SG13G2 130nm CMOS Technology
 
-SG13G2 is the name of a 130nm CMOS technology (strictly speaking BiCMOS) from IHP Microelectronics. It features low-voltage (thin-oxide) core MOSFET, high-voltage (thick-oxide) I/O MOSFET, various types of linear resistors, and 7 layers of Aluminium metallization (5 thin, 2 thick metal layers). This PDK is open-source, and the complete process specification can be found at [SG13G2 process specification](https://github.com/IHP-GmbH/IHP-Open-PDK/blob/main/ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf). While we will not do layouts in this course, the layout rules can be found at [SG13G2 layout rules](https://github.com/IHP-GmbH/IHP-Open-PDK/blob/main/ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf).
+SG13G2 is the name of a 130nm CMOS technology (strictly speaking BiCMOS) from IHP Microelectronics. It features low-voltage (thin-oxide) core MOSFET, high-voltage (thick-oxide) I/O MOSFET, various types of linear resistors, and 7 layers of Aluminium metallization (5 thin plus 2 thick metal layers). This PDK is open-source, and the complete process specification can be found at [SG13G2 process specification](https://github.com/IHP-GmbH/IHP-Open-PDK/blob/main/ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf). While we will not do layouts in this course, the layout rules can be found at [SG13G2 layout rules](https://github.com/IHP-GmbH/IHP-Open-PDK/blob/main/ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf).
 
 For our circuit design, the most important parameters of the available devices are summarized in the following:
 
@@ -20,18 +22,26 @@ For our circuit design, the most important parameters of the available devices a
 * **Poly resistor**: Device `rppd`; $R_\square=260\,\Omega \pm 10\%$, $\mathrm{TC}_1=170\,\text{ppm/K}$
 * **Poly resistor high**: Device `rhigh`; $R_\square=1360\,\Omega \pm 15\%$, $\mathrm{TC}_1=-2300\,\text{ppm/K}$ 
 * **MIM capacitor**: Device `cap_cmim`; $C'=1.5\,\text{fF}/\mu\text{m}^2 \pm 10\%$, $\mathrm{VC}_1=-26\text{ppm/V}$, $\mathrm{TC}_1=3.6\text{ppm/K}$, breakdown voltage $>15\,\mathrm{V}$
-* **MOM capacitor**: Well-suited metal stack due to 5 thin metal layers, but no primitive capacitor available.
+* **MOM capacitor**: The metal stack is well-suited for MOM capacitors due to 5 thin metal layers, but no primitive capacitor device is available at this point.
 
 ### Schematic Entry Using Xschem
 
-Xschem is an open-source schematic entry tool with emphasis on integrated circuits. For up-to-date information of the many features of Xschem please look at the [online documentation](https://xschem.sourceforge.io/stefan/xschem_man/xschem_man.html). Usage of Xschem will be learned with the first few basic examples, essentially a single MOSFET. The usage model of Xschem is that the schematic is hierarchically drawn, and the simulation and evaluation statements are contained in the schematics. Further, Xschem offers embedded graphing, which we will mostly use.
+Xschem is an open-source schematic entry tool with emphasis on integrated circuits. For up-to-date information of the many features of Xschem and the basic operation of it please look at the available [online documentation](https://xschem.sourceforge.io/stefan/xschem_man/xschem_man.html). Usage of Xschem will be learned with the first few basic examples, essentially using a single MOSFET. The usage model of Xschem is that the schematic is hierarchically drawn, and the simulation and evaluation statements are contained in the schematics. Further, Xschem offers embedded graphing, which we will mostly use.
 
 ### Circuit Simulation Using ngspice
 
-ngspice is an open-source circuit simulator with SPICE dependency. Besides the usual simulated types like `op` (operating point), `dc` (dc sweeps), `tran` (time-domain), or `ac` (for small-signal frquency sweeps), ngspice offers a script-like control interface, where many different simulation controls and result evaluations can be done. For detailed information please refer to the latest [manual](https://ngspice.sourceforge.io/docs/ngspice-43-manual.pdf).
+ngspice is an open-source circuit simulator with SPICE dependency [@Nagel_1975]. Besides the usual simulated types like `op` (operating point), `dc` (dc sweeps), `tran` (time-domain), or `ac` (small-signal frquency sweeps), ngspice offers a script-like control interface, where many different simulation controls and result evaluations can be done. For detailed information please refer to the latest [online manual](https://ngspice.sourceforge.io/docs/ngspice-43-manual.pdf).
 
 ### Integrated IC Design Environment (IIC-OSIC-TOOLS)
 
-In order to make usage of the various required components (tools like Xschem, PDK like SG13G2) easier, we will use the IIC-OSIC-TOOLS. This is a pre-setup Docker image which allows to design on a virtual machine on virtually any type of computing equipment. For further information like installed tools, how to setup a VM, etc. please look at [IIC-OSIC-TOOLS GitHub page](https://github.com/iic-jku/IIC-OSIC-TOOLS).
+In order to make use of the various required components (tools like Xschem and ngspice, PDKs like SG13G2) easier, we will use the **IIC-OSIC-TOOLS**. This is a pre-compiled Docker image which allows to do circuit design on a virtual machine on virtually any type of computing equipment (personal PC, Raspberry Pi, cloud server) on various operating systems (Windows, macOS, Linux). For further information like installed tools, how to setup a VM, etc. please look at [IIC-OSIC-TOOLS GitHub page](https://github.com/iic-jku/IIC-OSIC-TOOLS).
 
-Experienced users can install this image on their personal computer, for JKU students the IIC will host a VM on our compute cluster and provide personal login credentials.
+::: {.callout-tip}
+Please make sure to receive information about your personal VM access ahead of the course start.
+:::
+
+Experienced users can install this image on their personal computer, for JKU students the IIC will host a VM on our compute cluster and provide personal login credentials.
+
+::: {.callout-note}
+In this course, we assume that students have a basic knowledge of Linux and how to operate it using the terminal. If you are not yet familiar with Linux (which is basically a must when doing integrated circuit design as many tools are only available on Linux), then please check out a Linux introductory course or tutorial online, there are many ressources available.
+:::

figures/_fig_mosfet_diode.qmd

@@ -4,11 +4,13 @@
 #| fig-cap: "A MOSFET connected as a diode."
 import schemdraw as sd
 import schemdraw.elements as elm
-with sd.Drawing(canvas='svg'):
+with sd.Drawing(canvas='svg') as d:
+    d.config(unit=2)
+    d.config(fontsize=16)
     elm.Vdd()
     elm.SourceI().down().label(r'$I_\mathrm{bias}$', ofst=-2)
     elm.Dot()
-    M1 = elm.AnalogNFet().drop('source').theta(0).reverse().label('$W/L$', loc='right')
+    M1 = elm.AnalogNFet(offset_gate=False).drop('source').theta(0).reverse().label('$W/L$', loc='right')
     elm.Ground()
     elm.Line().left().at(M1.gate).length(0.5)
     elm.Line().up().toy(M1.drain)

figures/_fig_mosfet_large_signal_model.qmd

@@ -4,14 +4,22 @@
 #| fig-cap: "The MOSFET large-signal model."
 import schemdraw as sd
 import schemdraw.elements as elm
-with sd.Drawing(canvas='svg'):
-    elm.Vdd()
-    elm.SourceI().down().label(r'$I_\mathrm{bias}$', ofst=-2)
-    elm.Dot()
-    M1 = elm.AnalogNFet().drop('source').theta(0).reverse().label('$W/L$', loc='right')
-    elm.Ground()
-    elm.Line().left().at(M1.gate).length(0.5)
-    elm.Line().up().toy(M1.drain)
-    elm.Line().right().to(M1.drain)
-    elm.Arrow().at(M1.drain, dx=1.5).down().length(2).label(r'$V_\mathrm{GS}$', ofst=-1)
+with sd.Drawing(canvas='svg') as d:
+    d.config(unit=2)
+    d.config(fontsize=16)
+    d.push()
+    elm.Line().left().length(1).dot(open=True).label('G', 'left').idot()
+    d.pop()
+    d.push()
+    Cgs = elm.Capacitor().down().label(r'$C_\mathrm{GG}$')
+    elm.Line().right().length(6).dot()
+    l1 = elm.Line().down().length(1).dot(open=True).label('S', 'left')
+    d.pop()
+    Cgd = elm.Capacitor().right().length(6).label(r'$C_\mathrm{GD}$').dot()
+    d.push()
+    Ids = elm.SourceI().down().label(r'$I_\mathrm{DS} = f(V_\mathrm{GS}, V_\mathrm{DS}, V_\mathrm{SB})$')
+    d.pop()
+    elm.Line().right().dot(open=True).length(2).label('D', 'right')
+    d.move(dy=-2, dx=0)
+    elm.Line().down().toy(l1.end).dot(open=True).label('B', 'left')
 ```

figures/_fig_mosfet_small_signal_model.qmd

@@ -0,0 +1,35 @@
+```{python}
+#| label: fig-mosfet-small-signal-model
+#| echo: false
+#| fig-cap: "The MOSFET small-signal model."
+import schemdraw as sd
+import schemdraw.elements as elm
+with sd.Drawing(canvas='svg') as d:
+    d.config(unit=2)
+    d.config(fontsize=16)
+    d.push()
+    elm.Line().left().length(1).dot(open=True).label('G', 'left').idot()
+    d.pop()
+    d.push()
+    Cgs = elm.Capacitor().down().label(r'$C_\mathrm{gg}$')
+    elm.Line().right().length(3).dot()
+    l1 = elm.Line().down().length(1).dot(open=True).label('S', 'left')
+    d.pop()
+    Cgd = elm.Capacitor().right().length(3).label(r'$C_\mathrm{gd}$').dot()
+    d.push()
+    Ids1 = elm.SourceI().down().label(r'$g_\mathrm{m} \cdot v_\mathrm{gs}$')
+    elm.Line().right().length(3).dot()
+    d.push()
+    Ids2 = elm.SourceI().up().label(r'$g_\mathrm{mb} \cdot v_\mathrm{sb}$').dot()
+    d.pop()
+    elm.Line().right().length(3).dot()
+    d.push()
+    Rds = elm.Resistor().up().dot().label(r'$g_\mathrm{ds}$')
+    d.pop()
+    elm.Line().right().length(3)
+    In = elm.SourceSin().up().label(r'$\overline{I_\mathrm{n}^2}$').dot()
+    d.pop()
+    elm.Line().right().dot(open=True).length(12).label('D', 'right')
+    d.move(dy=-2, dx=0)
+    elm.Line().down().toy(l1.end).dot(open=True).label('B', 'left')
+```

figures/_fig_nmos_symbol.qmd

@@ -0,0 +1,15 @@
+```{python}
+#| label: fig-nmos-symbol
+#| echo: false
+#| fig-cap: "Circuit symbol of n-channel MOSFET."
+import schemdraw as sd
+import schemdraw.elements as elm
+with sd.Drawing(canvas='svg') as d:
+    d.config(unit=2)
+    d.config(fontsize=16)
+    M1 = elm.AnalogNFet(bulk=True,offset_gate=False).drop('source').theta(0).reverse()
+    elm.Line().up().at(M1.drain).length(0.5).dot(open=True).label('D', 'right')
+    elm.Line().down().at(M1.source).length(0.5).dot(open=True).label('S', 'left')
+    elm.Line().left().at(M1.gate).length(0.5).dot(open=True).label('G', 'left')
+    elm.Line().right().at(M1.bulk).length(0.5).dot(open=True).label('B', 'right')
+```

figures/_fig_pmos_symbol.qmd

@@ -0,0 +1,15 @@
+```{python}
+#| label: fig-pmos-symbol
+#| echo: false
+#| fig-cap: "Circuit symbol of p-channel MOSFET."
+import schemdraw as sd
+import schemdraw.elements as elm
+with sd.Drawing(canvas='svg') as d:
+    d.config(unit=2)
+    d.config(fontsize=16)
+    M1 = elm.AnalogPFet(bulk=True,offset_gate=False).drop('source').theta(0).reverse()
+    elm.Line().down().at(M1.drain).length(0.5).dot(open=True).label('D', 'left')
+    elm.Line().up().at(M1.source).length(0.5).dot(open=True).label('S', 'right')
+    elm.Line().left().at(M1.gate).length(0.5).dot(open=True).label('G', 'left')
+    elm.Line().right().at(M1.bulk).length(0.5).dot(open=True).label('B', 'right')
+```

index.qmd

@@ -8,6 +8,13 @@ author:
           city: Linz
           state: Austria
           url: www.jku.at
+    - name: Michael Koefinger
+      email: [email protected]
+      affiliations:
+        - name: Johannes Kepler University
+          city: Linz
+          state: Austria
+          url: www.jku.at 
 date: last-modified
 bibliography: references.bib
 ---

references.bib

@@ -1,16 +1,40 @@
 %% This BibTeX bibliography file was created using BibDesk.
-%% https://bibdesk.sourceforge.io/
+%% http://bibdesk.sourceforge.net/
 
-%% Created for Harald Pretl at 2024-07-27 18:08:11 +0200 
+%% Created for Harald Pretl at 2024-08-02 12:05:58 +0200 
 
 
 %% Saved with string encoding Unicode (UTF-8) 
 
 
 
+@phdthesis{Nagel_1975,
+	author = {Nagel, Laurence W.},
+	month = {May},
+	number = {UCB/ERL M520},
+	school = {EECS Department, University of California, Berkeley},
+	title = {SPICE2: A Computer Program to Simulate Semiconductor Circuits},
+	url = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1975/9602.html},
+	year = {1975},
+	bdsk-url-1 = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1975/9602.html}}
+
 @book{Jespers_Murmann_2017,
 	author = {Jespers, Paul G. A. and Murmann, Boris},
 	place = {Cambridge},
 	publisher = {Cambridge University Press},
 	title = {Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables},
 	year = {2017}}
+
+@book{Chenming_Hu_2010,
+	author = {Hu, Chenming},
+	place = {Upper Saddle River},
+	publisher = {Pearson},
+	title = {Modern Semiconductor Devices for Integrated Circuits},
+	year = {2010}}
+
+@book{Tsividis_McAndrew_2011,
+	author = {Tsividis, Yannis and McAndrew, Colin},
+	place = {New York},
+	publisher = {Oxford University Press},
+	title = {Operation and Modeling of the MOS Transistor},
+	year = {2011}}