Reduce all section hierarchies by one, add titles to all callout boxes

_sec_basic_ota.qmd

@@ -8,7 +8,7 @@ We note that $M_{1,2}$ and $M_{3,4}$ need to be symmetric, thus will have the sa
 
 As this is an OTA the output is a current; if the load impedance is high (i.e., purely capacitive, which is often the case in integrated circuits when driving MOSFET inputs) then the voltage gain of the OTA can be high (of course, in this simple OTA it is limited). With a high-impedance loading this OTA can provide a voltage output, and this is actually how OTAs are mostly operated.
 
-### Voltage Buffer with OTA
+## Voltage Buffer with OTA
 
 In order to design an OTA we need an application, and from this we need to derive the circuit specifications. We want to use this OTA to realize a voltage buffer which lighly loads a voltage source and can drive a large capacitive load. Such a configuration is often used to, e.g., buffer a reference voltage that is needed (and thus loaded) by another circuit. The block diagram of this configuration is shown in @fig-voltage-buffer-ota.
 
@@ -32,7 +32,7 @@ If the voltage gain of the OTA is @fig-voltage-buffer-ota is high, then $V_\math
 
 : Voltage buffer specification {#tbl-voltage-buffer-spec}
 
-### Large-Signal Analysis of the OTA {#sec-basic-ota-large-signal}
+## Large-Signal Analysis of the OTA {#sec-basic-ota-large-signal}
 
 The first step when receiving a design task is to look at the specifications, and see whether they make sense. Detailed performance of the design will be the result of the circuit simulation, but before we step into sizing we need to do a few simple calculations to (a) allows to do back-of-the-envelope gauging if the specification makes sense, and (b) the derived analytical equations will serve as guide for the sizing procedure.
 
@@ -55,7 +55,7 @@ T_\mathrm{slew} \approx \frac{5}{2 \pi f_\mathrm{c}} = \frac{5}{2 \pi \cdot 1 \c
 $$
 which also checks out.
 
-### Small-Signal Analysis of the OTA {#sec-basic-ota-small-signal}
+## Small-Signal Analysis of the OTA {#sec-basic-ota-small-signal}
 
 In order to size the OTA components we need to derive how MOSFET parameters define the performance. The important small-signal metrics are
 
@@ -70,7 +70,7 @@ $$
 
 So in order to reach an output voltage accuracy of at least 3% we need a dc gain of $A_0 > 30.2\,\text{dB}$. To allow for process and temperature variation we need to add a bit of extra gain as margin. 
 
-#### OTA Small-Signal Transfer Function
+### OTA Small-Signal Transfer Function
 
 In order to derive the governing equations for the OTA we will make a few simplifications:
 
@@ -81,7 +81,7 @@ In order to derive the governing equations for the OTA we will make a few simpli
 
 The resulting small-signal equivalent circuit is shown in @fig-basic-ota-small-signal.
 
-::: {.callout-note}
+::: {.callout-warning title="Refresh MOSFET Small-Signal Model"}
 Please review the MOSFET small-signal equivalent model in @fig-mosfet-small-signal-model at this point. For the PMOS just flip the model upside-down.
 :::
 
@@ -129,7 +129,7 @@ $$
 s_\mathrm{zd} = -\frac{2 \gm[34]}{\Cgs[34]}
 $$
 
-#### OTA Noise
+### OTA Noise
 
 For the noise analysis we ignore the pole-zero doublet due to $\Cgs[34]$ (we assume minor impact due to this) and just consider the dominant pole. For the noise analysis at the output we set the input signal to zero, and thus we arrive at the simplified small-signal circuit shown in @fig-basic-ota-small-signal-noise.
 
@@ -140,7 +140,7 @@ $$
 \overline{\Vgs[34]^2} = \frac{1}{\gm[34]^2} \left( \overline{I_\mathrm{n1}^2} + \overline{I_\mathrm{n3}^2} \right).
 $$
 
-::: {.callout-note}
+::: {.callout-important title="Noise Addition"}
 Remember that **uncorrelated** noise quantities need to be power-summed (i.e., $I^2 = I_1^2 + I_2^2$)!
 :::
 
@@ -175,37 +175,37 @@ $$ {#eq-basic-ota-output-noise}
 
 Inspecting @eq-basic-ota-output-noise we can see that the integrated output noise is the $k T / C$ noise of the output load capacitor, enhanced by the $\gamma_{12}$ of the input differential pair, plus a (smaller) contribution of the current mirror load $M_{3,4}$. Intuitevly, this result makes sense.
 
-::: {.callout-tip title="Exercise"}
+::: {.callout-tip title="Exercise: Derivation of 5T-OTA Performance"}
 Please take your time and carefully go through the explanations and derivations for the 5-transistor-OTA in @sec-basic-ota-large-signal and @sec-basic-ota-small-signal. Try to do the calculations yourself; if you get stuck, review the previous chapters.
 :::
 
-### 5T-OTA Sizing
+## 5T-OTA Sizing
 
 Outfitted with the governing equations derived in @sec-basic-ota-small-signal we can now size the MOSFETs in the OTA, we remember that we have to size $M_{1,2}$ and $M_{3,4}$ equally.
 
 First, we need to select a proper $\gmid$ for the MOSFET. Remembering @sec-gmid-method we see that for the input differential pair we should go for a large $\gm$, thus we select a $\gmid = 10$. As $\gds$ of $M_2$ could limit the dc gain (@eq-simple-ota-gain-dc) we go with a rather long $L = 5\,\mu\text{m}$. For current sources a small $\gmid$ is a good idea, so we start with $\gmid=5$ (because we can not go too low because of $V_\mathrm{ds,sat}$) and also an $L = 5\,\mu\text{m}$.
 
-::: {.callout-tip title="Exercise"}
+::: {.callout-tip title="Exercise: 5T-OTA Sizing"}
 Please size the 5T-OTA according to the previous $\gmid$ and $L$ suggestions. Please calculate the $W$ of $M_{1-6}$ and the total supply current. Please check wether gain error, total output noise, and turn-on settling is met with the calculated devices sizes and bias currents.
 :::
 
 The sizing procedure and its calculation are best performed in a Jupyter notebook, as we can easily look up the exact data from the pre-computed tables:
 
-::: {.callout-note}
+::: {.callout-tip title="Solution: 5T-OTA Sizing" collapse="true"}
 {{< embed ./sizing/sizing_basic_ota.ipynb echo=true >}}
 :::
 
-### 5T-OTA Simulation {#sec-basic-ota-simulation}
+## 5T-OTA Simulation {#sec-basic-ota-simulation}
 
-With the initial sizing of the MOSFETs of the 5T-OTA done, we can setup a simulation testbench and check the performance parameters.
+With the initial sizing of the MOSFETs of the 5T-OTA done, we can design the 5T-OTA circuit and setup a simulation testbench to check the performance parameters.
 
-::: {.callout-tip title="Exercise"}
-Please setup a testbench in Xschem for the 5T-OTA used as a voltage buffer as schown in @fig-voltage-buffer-ota. Use typical conditions for the simulation, and check how well the specification in @tbl-voltage-buffer-spec is met, and how well the derivations in @sec-basic-ota-large-signal and @sec-basic-ota-small-signal fit to the simulation results.
+::: {.callout-tip title="Exercise: 5T-OTA Design and Testbench"}
+Please design the circuit of the 5T-OTA. Put the OTA circuit in a separate schematic, create a symbol for it, and use this symbol in a testbench you create in Xschem for this 5T-OTA used as a voltage buffer as schown in @fig-voltage-buffer-ota. Use typical conditions for the simulation, and check how well the specification in @tbl-voltage-buffer-spec is met, and how well the derivations in @sec-basic-ota-large-signal and @sec-basic-ota-small-signal fit to the simulation results.
 
-If you get stuck, you can find the tesbench [here](./xschem/ota-5t_tb-ac.svg) (for the small-signal analysis) and [here](./xschem/ota-5t_tb-ac.svg) (for the large-signal settling simulation).
+If you get stuck, you can find the testbench and 5T-OTA schematic [here](./xschem/ota-5t_tb-ac.svg) (for the small-signal analysis) and [here](./xschem/ota-5t_tb-ac.svg) (for the large-signal settling simulation).
 :::
 
-### 5T-OTA Simulation versus PVT
+## 5T-OTA Simulation versus PVT
 
 As you have seen in @sec-basic-ota-simulation running simulations by hand is tedious. When we want to check the overall performance, we have to run many simulations over various conditions:
 
@@ -226,10 +226,11 @@ There is a CACE setup available for our 5T-OTA. The [datasheet](./cace/voltage-b
 
 After a successul run, a documentation is automatically generated. The result of a full run of this [OTA design](./xschem/ota-5t.svg) is presented here:
 
-::: {#nte-basic-ota-cace-result .callout-note}
+::: {#nte-basic-ota-cace-result .callout-note title="CACE Summary for 5T-OTA"}
+
 {{< include ./cace/_docs/ota-5t_schematic.md >}}
 :::
 
-#### PVT Simulation Analysis
+### PVT Simulation Analysis
 
 Looking at the CACE report in @nte-basic-ota-cace-result we see that (luckily) the specifiction is met for all parameters. This is great news! We now have a design that we carefully simulated across PVT and other corners, and which is ready for layout. Once we have the layout ready, we can extract the wiring parasitics ($R$ and $C$) as well as other layout-dependent effects like [well proximity](https://global.oup.com/us/companion.websites/9780195170153/pdf/proximityeffectmodels.pdf). Using this augmented netlist we can then again use CACE to check performance across conditions and parameter variations, and if we still pass all specification points then our design is finished.

_sec_current_mirror.qmd

@@ -15,7 +15,7 @@ For good matching in layout care has to be taken that the MOSFET widths and leng
 
 As we know from earlier investigations of the MOSFET performance in @sec-gmid-method the drain current of a MOSFET is a function of $\VGS$ and $\VDS$. As long as the MOSFET stays in saturation (i.e., $\VDS > V_\mathrm{ds,dsat}$) the drain current is just a mild function of $\VDS$ (essentially the effect of $\gds$, which is the output conductance of the MOSFET). A fundamental flaw of the basic current mirror shown in @fig-current-mirror is the mismatch of the $\VDS$ of the MOSFET. The input-side diode has $\VGS = \VDS$, whereas the output current sources have a $\VDS$ depending on the connected circuitry. Improved current mirrors exist (basically fixing this flaw), still, when just a simple current mirror is required this structure is used for its simplicity.
 
-::: {.callout-tip title="Exercise"}
+::: {.callout-tip title="Exercise: Current Mirror"}
 Please construct a current mirror based on the MOSFET-diode which we sized in @sec-mosfet-diode. The input current $I_\mathrm{bias} = 20\,\mu\text{A}$, and we want three output currents of size $10\,\mu\text{A}$, $20\,\mu\text{A}$, and $40\,\mu\text{A}$.
 
 Sweep the output voltage of all three current branches and see over which voltage range an acceptable current is created. For which output voltage range is the current departing from its ideal value, and why?

_sec_differential_pair.qmd

@@ -4,7 +4,7 @@ Like the current mirror in @sec-current-mirror the **differential pair** is an u
 
 In order to understand its operation it is instructive to separate the input condition into (1) a purely differential voltage, and (2) into a common-mode voltage, and see what the impact on the output currents is.
 
-### Differential Operation of the Diffpair
+## Differential Operation of the Diffpair
 
 For a differential mode of operation we assume that the input common mode voltage is constant, i.e. $V_\mathrm{in,p} + V_\mathrm{in,n} = V_\mathrm{CM}$. A differential input voltage $v_\mathrm{in}$ then results in
 $$
@@ -31,7 +31,7 @@ $$ {#eq-differential-pair-dm}
 
 We see in @eq-differential-pair-dm that the differential output current is simply the differential input voltage multiplied by the $\gm$ of the individual transistor. We also note that the bottom conductance $g_\mathrm{tail}$ plays no role for the small-signal differential operation.
 
-### Common-Mode Operation of the Diffpair
+## Common-Mode Operation of the Diffpair
 
 Usually, the source conductance $g_\mathrm{tail}$ is realized by a current source and ideally should be $g_\mathrm{tail} = 0$. If this is the case, then the output currents are not a function of the common-mode input voltage, and ($I_\mathrm{tail}$ is set by the tail current source)
 $$

_sec_first_steps.qmd

@@ -1,12 +1,12 @@
 In this first chapter we will learn to use Xschem for schematic entry, and how to operate the ngspice SPICE simulator for circuit simulations. Further, we will make ourself familiar with the transistor and other passive components available in the IHP Microelectronics SG13G2 technology. While this is strictly speaking a BiCMOS technology offering MOSFETs as well as SiGe HBTs, we will use it as a pure CMOS technology.
 
-### The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) {#sec-mosfet}
+## The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) {#sec-mosfet}
 
 In this course, we will not dive into semiconductor physics and derive the device operation bottom-up starting from a fundamental level governed by quantum mechanics. Instead, we will treat the MOSFET as a macroscopic by assuming we have a 4-terminal device, and the performance of this device regarding its terminal voltages and currents we will largely derive from the simulation model. 
 
 The circuit symbol that we will use for the n-channel MOSFET is shown in @fig-nmos-symbol, and for the p-channel MOSFET it is shown in @fig-pmos-symbol. A control voltage between gate ("G") and source ("S") causes a current to flow between drain ("D") and source. The MOSFET is a 4-terminal device, so the bulk ("B") can also control the drain-source current flow. Often, the bulk is connected to source, and then the bulk terminal is not shown to declutter the schematics.
 
-::: {.callout-note}
+::: {.callout-note title="MOSFET Background"}
 Strictly speaking is the drain-source current of a MOSFET controlled by the voltage between gate and bulk and the voltage between drain and source. Since bulk is often connected to source anyway, and many circuit designers historically were already familiar with the operation of the bipolar junction transistor, it is common to consider the gate-source voltage (besides the drain-source voltage) as the controlling voltage.
 
 This focus on gate-source implies that the source is special compared to the drain. In a typical physical MOSFET, however, the drain and source are constructed exactly the same, and which terminal is drain, and which terminal is source, is only determined by the applied voltage potentials, and can change dynamically during operation (think of a MOSFET operating as a switch... which side is the drain, which side is the source?).
@@ -23,7 +23,7 @@ For hand calculations and theoretical discussions we will use the following simp
 
 In an ideal MOSFET no dc current is flowing into the gate, the behavior is purely capacitive. We model this by two capacitors: $\CGG = \CGS + \CGD$ is the total capacitance when looking into the gate of the MOSFET. $\CGS$ is usually the dominant capacitance, and $\CGD$ models the capacitive feedback between D and G, usually induced by a topological overlap capacitance in the physical construction of the MOSFET. This capacitance is often small compared to $\CGS$, but in situations where we have a large voltage swing at the drain this capacitance will be affected by the [Miller effect](https://en.wikipedia.org/wiki/Miller_effect). In hand calculations we will often set $\CGD = 0$.
 
-::: {.callout-note}
+::: {.callout-note title="MOSFET Bulk Terminal"}
 The bulk connection in @fig-mosfet-large-signal-model seems floating as we only consider it a control terminal, where the potential difference between source and bulk influences the behaviour of the MOSFET. However, we do not consider resistive or capacitive effects associated with this node, which is of course a gross simplification, but nevertheless one we will make in this course.
 :::
 
@@ -33,8 +33,8 @@ As a side note, the students who want to understand MOSFET behaviour from a phys
 
 Now, in order to get started, basic Xschem testbenches are prepared, and first simple dc sweeps of various voltages and currents will be done. But before that, please look at the import note below!
 
-::: {.callout-important}
-Throughout this material, we will stick to the following notations:
+::: {.callout-important title="Mathematical Notation"}
+Throughout this material, we will largely stick to the following notation:
 
 * A **dc quantity** is shown with an upper-case letter with upper-case subscripts, like $\VGS$.
 * Double-subscripts denote **dc sources**, like $\VDD$ and $\VSS$.
@@ -43,13 +43,13 @@ Throughout this material, we will stick to the following notations:
 * A upper-case letter with a lower-case subscript is used to denote **RMS quantities**, like $I_\mathrm{ds}$.
 :::
 
-#### Large-Signal MOSFET Model
+### Large-Signal MOSFET Model
 
 We start with an investigation into the large-signal MOSFET model shown in @fig-mosfet-large-signal-model by using the simple testbench for the LV NMOS shown in @fig-simple-nmos-tb.
 
 ![Testbench for NMOS dc sweeps.](./xschem/dc_lv_nmos.svg){#fig-simple-nmos-tb}
 
-::: {.callout-tip title="Exercise"}
+::: {.callout-tip title="Exercise: MOSFET Investigation"}
 Please try to execute the following steps and answer these questions:
 
 1. Get the LV NMOS testbench (available at <https://github.com/iic-jku/analog-circuit-design/blob/main/xschem/dc_lv_nmos.sch>) working in your IIC-OSIC-TOOLS environment.
@@ -67,7 +67,7 @@ Please try to execute the following steps and answer these questions:
    1. What happens when $V_\mathrm{BS} \neq 0$?
 :::
 
-#### Small-Signal MOSFET Model {#sec-mosfet-smallsignal-model}
+### Small-Signal MOSFET Model {#sec-mosfet-smallsignal-model}
 
 As you have seen in the previous investigations, the large-signal model of @fig-mosfet-large-signal-model describes the behaviour of the MOSFET across a wide range of voltages applied at the MOSFET terminals. Unfortunately, for hand analysis dealing with a nonlinear model is close to impossible, at the very least it is quite tedious.
 
@@ -83,13 +83,13 @@ $$
 $$ {#eq-mosfet-noise}
 where $\overline{I_\mathrm{n}^2}$ is the power-spectral density of the noise in A$^2$/Hz; $k$ is the Boltzmann constant; $T$ is the absolute temperature; $\gamma$ is a parameter in simplified theory changing between $\gamma = 2/3$ in saturation and $\gamma =1$ for triode operation; $g_\mathrm{d0}$ is equal to $\gm$ in saturation and $\gds$ in triode).
 
-::: {.callout-note}
+::: {.callout-note title="MOSFET Triode and Saturation Region"}
 Sometimes we will refer to different operating modes of the MOSFET like "saturation" or "triode". Generally speaking, when the drain-source voltage is small, then the MOSFET acts as a resistor, and this mode of operation we call "triode" mode. When the drain-source voltage is increased, at some point the drain-source current saturates and is no longer a strong function of the drain-source voltage. This mode is called "saturation" mode. As you can see in the large-signal investigations, these transitions happen gradually, and it is difficult to define a precise point where one operating mode switches to the other one. In this sense we use terms like "triode" and "saturation" only in an approximative sense.
 :::
 
 Now we need to see how the small-signal parameters seen in @fig-mosfet-small-signal-model can be investigated and estimated using circuit simulation.
 
-::: {.callout-tip title="Exercise"}
+::: {.callout-tip title="Exercise: MOSFET Small-Signal Parameters"}
 Please try to execute the following steps and answer the following questions:
 
 1. Reuse the LV NMOS testbench (available at <https://github.com/iic-jku/analog-circuit-design/blob/main/xschem/dc_lv_nmos.sch>).
@@ -102,6 +102,6 @@ Please try to execute the following steps and answer the following questions:
    1. What is the difference in $\gm$, $\gds$, and other parameters between the NMOS and the PMOS? Why could they be different?
 :::
 
-### Conclusion
+## Conclusion
 
 Congratulations for making it thus far! By now you should have a solid grasp of the tool handling of Xschem and ngspice, and you should be familiar with the large- and small-signal operation of both NMOS and PMOS, and the parameters describing these behaviours. If you feel you are not sufficiently fluent in these things, please go back to the beginning of @sec-mosfet and revisit the relevant sections, or dive into further reading about the MOSFET operation, like in [@Chenming_Hu_2010].