Change SIM to SIMULATION

iic-jku · Mar 1, 2024 · 733b9df · 733b9df
1 parent f30f2f6
commit 733b9df
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/src/tempsens_core.v b/src/tempsens_core.v
@@ -29,10 +29,10 @@
 `define __TEMPSENS_CORE__
 
 `default_nettype none
-`ifdef SIM
+`ifdef SIMULATION
 `timescale 1ns/1ns
 `endif
-`ifndef SIM
+`ifndef SIMULATION
 `include "tempsens_vdac.v"
 `endif
 //`include "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
@@ -43,7 +43,7 @@ module tempsens_core #( parameter DAC_RESOLUTION=6, parameter CAP_LOAD=16 )(
       input wire [DAC_RESOLUTION-1:0]     i_dac_data,
       input wire                          i_dac_en,
       input wire                          i_precharge_n,
-`ifdef SIM
+`ifdef SIMULATION
       output reg                          o_tempdelay
 `else
       output wire                         o_tempdelay
@@ -53,7 +53,7 @@ module tempsens_core #( parameter DAC_RESOLUTION=6, parameter CAP_LOAD=16 )(
       // during precharging and measurement, o_tempdelay stays high
       // a 1->0 transition marks the end of the measurement time
 
-`ifdef SIM
+`ifdef SIMULATION
       wire dac0, dac1, dac_change;
       assign dac0 = ~|i_dac_data;
       assign dac1 = &i_dac_data;