[cortex-m7] Enable I/D-Cache via lbuild #1255
Open
+69
−45
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
salkinium
force-pushed
the
fix/dcache
branch
4 times, most recently
from
12a27d4 to
539a0bf
Compare
|
@jgmess-dlr Could you check if this change still works for your use case? I discovered stability issues when uploading using a JLINK. I think the main issue is that VTOR is set to RAM by default on Cortex-M4, but the VTOR may not actually have been copied to RAM and instead is still in DCache. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Only enable the D-Cache after the memory operations, so that all data is committed to the memory when required (for example for the VTOR in RAM!!!)
Related to #1236.