[AIE2P] Instruction select G_SELECT.

Xilinx · Jan 23, 2025 · f8c5009 · f8c5009
1 parent bd09bc6
commit f8c5009
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diff --git a/llvm/lib/Target/AIE/aie2p/AIE2PInstrPatterns.td b/llvm/lib/Target/AIE/aie2p/AIE2PInstrPatterns.td
@@ -981,6 +981,11 @@ def : Pat<(int_aie2p_vneg_gtz16 VEC512:$s1), (VNEG_GTZ_16 VEC512:$s1)>;
 def : Pat<(int_aie2p_vneg_gtz32 VEC512:$s1), (VNEG_GTZ_32 VEC512:$s1)>;
 
 // VSEL
+foreach vec512Ty = [v64i8, v32i16, v16i32] in {
+  def : Pat<(vec512Ty (select (i32 eR:$rs1), VEC512:$rs2, VEC512:$rs3)),
+            (vec512Ty (VSEL_32 VEC512:$rs2, VEC512:$rs3, (ADD_add_r_ri eR:$rs1, (i32 -1))))>;
+}
+
 def : Pat<(int_aie2p_vsel8 VEC512:$src1, VEC512:$src2, eL:$lsel),
            (VSEL_8 VEC512:$src1, VEC512:$src2, eL:$lsel)>;
 

diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-select.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-select.mir
@@ -57,3 +57,28 @@ body: |
     $p0 = COPY %5
 ...
 
+---
+name:            select_512vec
+alignment:       16
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.1.entry:
+    liveins: $r0, $x0, $x1
+    ; CHECK-LABEL: name: select_v32s16
+    ; CHECK: liveins: $r0, $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x1
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
+    ; CHECK-NEXT: [[ADD_add_r_ri:%[0-9]+]]:ers16 = ADD_add_r_ri [[COPY2]], -1, implicit-def dead $srcarry
+    ; CHECK-NEXT: [[VSEL_32_:%[0-9]+]]:vec512 = VSEL_32 [[COPY]], [[COPY1]], [[ADD_add_r_ri]]
+    ; CHECK-NEXT: $x0 = COPY [[VSEL_32_]]
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
+    %1:vregbank(<32 x s16>) = COPY $x0
+    %2:vregbank(<32 x s16>) = COPY $x1
+    %3:gprregbank(s32) = COPY $r0
+    %0:vregbank(<32 x s16>) = G_SELECT %3:gprregbank(s32), %1:vregbank(<32 x s16>), %2:vregbank(<32 x s16>)
+    $x0 = COPY %0:vregbank(<32 x s16>)
+    PseudoRET implicit $lr, implicit $x0
+...